Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure

Abstract: A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period.

Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.

Abstract: The present invention provides a data processing apparatus and method for translating a signal between a first clock domain and a second clock domain. The data processing apparatus may comprise a first component for generating a signal, the first component operating in the first clock domain having a first clock period, and a second component for receiving the signal, the second component operating in the second clock domain having a second clock period. In one embodiment, the second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component.

Abstract: A data processing apparatus comprising at least one initiator operable to communicate with at least one recipient via a bus; said at least one initiator comprising an output port for sending data to said bus and an input port for receiving data from said bus; said data processing apparatus further comprising an initiator clock signal generator, an initiator output enable signal generator and an initiator input enable signal generator, said initiator being clocked by said initiator clock signal; said output port being clocked by said initiator output enable signal such that said output port is operable to assert data to a write channel on said bus in response to said initiator output enable signal having a first predetermined level and said input port is operable to latch data received on a read channel on said bus in response to said initiator input enable signal having a second predetermined level; wherein said initiator output enable signal generator and initiator input enable signal generator are configure

Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.