Patents by Inventor Pierre Mur
Pierre Mur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10276738Abstract: A heterojunction photovoltaic cell includes at least one crystalline silicon oxide film directly placed onto one of the front or rear faces of a crystalline silicon substrate, between said substrate and a layer of amorphous or microcrystalline silicon. The thin film is intended to enable the passivation of said face of the substrate. The thin film is more particularly obtained by radically oxidizing a surface portion of the substrate, before depositing the layer of amorphous silicon. Moreover, a thin layer of intrinsic or microdoped amorphous silicon can be placed between said think film and the layer of amorphous or microcrystalline silicon.Type: GrantFiled: January 26, 2011Date of Patent: April 30, 2019Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Pierre Mur, Hubert Moriceau, Pierre-Jean Ribeyron
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Publication number: 20150214392Abstract: The invention relates to a photovoltaic cell having a heterojunction, including a doped substrate (1), in which: a first main face (1A) of said substrate is covered with a passivation layer (2A), a doped layer (3A) of the type opposite to the substrate and forming the transmitter of said cell; the second main face (1B) of said substrate is covered with a passivation layer (2B), a doped layer (3B) of the same type as the substrate defining a repulsing field for the minor carriers of the substrate; characterized in that: the material of the passivation layer (2A) on the transmitter (E) side is selected so as to have a lower potential barrier for the photo-generated minor carriers than for the major carrier of the substrate; and in that the material of the passivation layer (2B) on the side of the repulsing field (BSF) is selected so as to have a lower potential barrier for all the photo-generated major carriers than for the minor carriers of the substrate.Type: ApplicationFiled: September 24, 2013Publication date: July 30, 2015Applicant: Commissariat à I ' Energie Atomique et aux Energies AlternativesInventors: Julien Buckley, Pierre Mur
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Patent number: 8877539Abstract: A method for producing of at least one photovoltaic cell includes successively the anisotropic etching of a surface of a crystalline silicon substrate and the isotropic etching treatment of said surface. The isotropic etching treatment includes at least two successive operations respectively consisting in forming a silicon oxide thin film with a controlled average thickness, ranging between 10 nm and 500 nm and in removing said thin film thus-formed. The operation consisting in forming a silicon oxide thin film on the face of the substrate is carried out by a thermally activated dry oxidation. Such a method makes it possible to improve the surface quality of the surface of the substrate once said surface is etched in an anisotropic way.Type: GrantFiled: January 26, 2011Date of Patent: November 4, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Hubert Moriceau, Pierre Mur, Pierre-Jean Ribeyron
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Patent number: 8815629Abstract: A method of manufacturing an optical reflector including an alternating stack of at least one first layer of complex refraction index n1 and at least one second layer of complex refraction index n2, in which the first layer includes semiconductor nanocrystals, including the following steps: calculation of the total number of layers of the stack, of the thicknesses of each of the layers and of the values of complex refraction indices n1 and n2 on the basis of the characteristics of a desired spectral reflectivity window of the optical reflector, including the use of an optical transfer matrices calculation method; calculation of deposition and annealing parameters of the layers on the basis of the total number of layers and of the values of previously calculated complex refraction indices n1 and n2; deposition and annealing of the layers in accordance with the previously calculated parameters.Type: GrantFiled: August 10, 2012Date of Patent: August 26, 2014Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Kavita Surana, Mathieu Baudrit, Pierre Mur, Philippe Thony
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Publication number: 20130052772Abstract: A method of manufacturing an optical reflector including an alternating stack of at least one first layer of complex refraction index n1 and at least one second layer of complex refraction index n2, in which the first layer includes semiconductor nanocrystals, including the following steps: calculation of the total number of layers of the stack, of the thicknesses of each of the layers and of the values of complex refraction indices n1 and n2 on the basis of the characteristics of a desired spectral reflectivity window of the optical reflector, including the use of an optical transfer matrices calculation method; calculation of deposition and annealing parameters of the layers on the basis of the total number of layers and of the values of previously calculated complex refraction indices n1 and n2; deposition and annealing of the layers in accordance with the previously calculated parameters.Type: ApplicationFiled: August 10, 2012Publication date: February 28, 2013Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALTInventors: Kavita Surana, Mathieu Baudrit, Pierre Mur, Philippe Thony
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Patent number: 8343855Abstract: The invention concerns a nanostructured device (100) comprising a substrate (101), an intermediate layer (102), a zone (103) consisting of multiple three-dimensional structured sites (104) made of semiconductor material, having chemical species (106) fixed to the surface of said three-dimensional nanostructured sites (104). The inventive device is useful for making a biochip and an electronic memory. The invention also concerns a method for forming an electronic memory.Type: GrantFiled: November 24, 2006Date of Patent: January 1, 2013Assignee: Commissariat A L'Energie AtomiqueInventors: Pierre Mur, Cécile Oillic
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Publication number: 20120291861Abstract: A heterojunction photovoltaic cell includes at least one crystalline silicon oxide film directly placed onto one of the front or rear faces of a crystalline silicon substrate, between said substrate and a layer of amorphous or microcrystalline silicon. The thin film is intended to enable the passivation of said face of the substrate. The thin film is more particularly obtained by radically oxidizing a surface portion of the substrate, before depositing the layer of amorphous silicon. Moreover, a thin layer of intrinsic or microdoped amorphous silicon can be placed between said think film and the layer of amorphous or microcrystalline silicon.Type: ApplicationFiled: January 26, 2011Publication date: November 22, 2012Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Pierre Mur, Hubert Moriceau, Pierre-Jean Ribeyron
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Publication number: 20120288985Abstract: A method for producing of at least one photovoltaic cell includes successively the anisotropic etching of a surface of a crystalline silicon substrate and the isotropic etching treatment of said surface. The isotropic etching treatment includes at least two successive operations respectively consisting in forming a silicon oxide thin film with a controlled average thickness, ranging between 10 nm and 500 nm and in removing said thin film thus-formed. The operation consisting in forming a silicon oxide thin film on the face of the substrate is carried out by a thermally activated dry oxidation. Such a method makes it possible to improve the surface quality of the surface of the substrate once said surface is etched in an anisotropic way.Type: ApplicationFiled: January 26, 2011Publication date: November 15, 2012Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Hubert Moriceau, Pierre Mur, Pierre-Jean Ribeyron
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Patent number: 7713850Abstract: Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals (13). It consists in: exposing with a beam of electrons (11) at least one zone (12) of a semiconductor film (1) lying on an electrically insulating support (2), the exposed zone (12) contributing to defining at least one dewetting zone (10) of the film (1), annealing the film (1) at high temperature in such a way that the dewetting zone (10) retracts giving the zone of one or several nanocrystals (13).Type: GrantFiled: July 19, 2005Date of Patent: May 11, 2010Assignee: Commissariat A l'Energie AtomiqueInventors: Maud Vinet, Jean-Charles Barbe, Pierre Mur, François De Crecy
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Publication number: 20090243048Abstract: A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a layer formed with process parameters that are not compatible with the integrity of unprotected metallic nanocrystals.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Inventors: Joel Dufourcq, Laurent Vandroux, Pierre Mur, Sylvie Bodnar
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Publication number: 20090246510Abstract: A device and method include forming a mask on a substrate supporting a plurality of metallic nanocrystals such that a portion of the metallic nanocrystals is exposed. Protective shells are formed about the exposed metallic nanocrystals. Unprotected metallic nanocrystals are removed.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE, ATMEL ROUSSETInventors: Joel Dufourcq, Laurent Vandroux, Pierre Mur, Sylvie Bodnar
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Publication number: 20090221447Abstract: The invention concerns a nanostructured device (100) comprising a substrate (101), an intermediate layer (102), a zone (103) consisting of multiple three-dimensional structured sites (104) made of semiconductor material, having chemical species (106) fixed to the surface of said three-dimensional nanostructured sites (104). The inventive device is useful for making a biochip and an electronic memory.Type: ApplicationFiled: November 24, 2006Publication date: September 3, 2009Inventors: Pierre Mur, Cécile Oillic
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Patent number: 7544547Abstract: The invention relates to a method for producing a support comprising nanoparticles (22) for the growth of nanostructures (23), said nanoparticles being organised periodically, the method being characterised in that it comprises the following steps: providing a support comprising, in the vicinity of one of its surfaces, a periodic array of crystal defects and/or stress fields (18), depositing, on said surface, a continuous layer (20) of a first material capable of catalysing the nanostructure growth reaction, fractionating the first material layer (20) by a heat treatment so as to form the first material nanoparticles (22).Type: GrantFiled: January 19, 2007Date of Patent: June 9, 2009Assignee: Commissariat a l'Energie AtomiqueInventors: Frank Fournel, Jean Dijon, Pierre Mur
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Publication number: 20080318366Abstract: The invention relates to a method for producing a support comprising nanoparticles (22) for the growth of nanostructures (23), said nanoparticles being organised periodically, the method being characterised in that it comprises the following steps: providing a support comprising, in the vicinity of one of its surfaces, a periodic array of crystal defects and/or stress fields (18), depositing, on said surface, a continuous layer (20) of a first material capable of catalysing the nanostructure growth reaction, fractionating the first material layer (20) by a heat treatment so as to form the first material nanoparticles (22). The invention also relates to a method for producing nanostructures from said support.Type: ApplicationFiled: January 19, 2007Publication date: December 25, 2008Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Frank Fournel, Jean Dijon, Pierre Mur
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Patent number: 7435690Abstract: Method of preparing a silicon dioxide layer by high-temperature oxidation on a substrate of formula Si1-xGex in which x is greater than 0 and less than or equal to 1, the said method comprising the following successive steps: a) at least one additional layer of thickness hy and of overall formula Si1-yGey, in which y is greater than 0 and less than x, is deposited on the said substrate of formula Si1-xGex; and b) the high-temperature oxidation of the said additional layer of overall formula Si1-yGey is carried out, whereby the said additional layer is completely or partly converted into a layer of silicon oxide SiO2. Method of preparing an optical or electronic component, comprising at least one step for preparing an SiO2 layer using the method described above.Type: GrantFiled: March 25, 2005Date of Patent: October 14, 2008Assignee: Commissariat a l'Energie AtomiqueInventors: Hubert Moriceau, Pierre Mur
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Publication number: 20060019459Abstract: Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals (13). It consists in: exposing with a beam of electrons (11) at least one zone (12) of a semiconductor film (1) lying on an electrically insulating support (2), the exposed zone (12) contributing to defining at least one dewetting zone (10) of the film (1), annealing the film (1) at high temperature in such a way that the dewetting zone (10) retracts giving the zone of one or several nanocrystals (13).Type: ApplicationFiled: July 19, 2005Publication date: January 26, 2006Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Maud Vinet, Jean-Charles Barbe, Pierre Mur, Francois De Crecy
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Publication number: 20050215071Abstract: Method of preparing a silicon dioxide layer by high-temperature oxidation on a substrate of formula Si1-xGex in which x is greater than 0 and less than or equal to 1, the said method comprising the following successive steps: a) at least one additional layer of thickness hy and of overall formula Si1-yGey, in which y is greater than 0 and less than x, is deposited on the said substrate of formula Si1-xGex; and b) the high-temperature oxidation of the said additional layer of overall formula Si1-yGey is carried out, whereby the said additional layer is completely or partly converted into a layer of silicon oxide SiO2. Method of preparing an optical or electronic component, comprising at least one step for preparing an SiO2 layer using the method described above.Type: ApplicationFiled: March 25, 2005Publication date: September 29, 2005Inventors: Hubert Moriceau, Pierre Mur
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Patent number: 6724017Abstract: The invention relates to a device comprising microstructures or nanostructures on a support, characterized in that the support comprises: a) a substrate (1) comprising at least one part composed of a crystalline material, this part having a surface (2) with a stress field or a topology associated with a stress field, the stress field being associated with dislocations, b) an intermediate layer (3) bonded to the surface (2), and having a thickness and/or composition and/or a surface state enabling transmission of said stress field through this layer as far as its free face that supports microstructures or nanostructures (4).Type: GrantFiled: March 28, 2003Date of Patent: April 20, 2004Assignees: Commissariat a l'Energie Atomique, Centre National de la Recherche ScientificInventors: Marie-Noëlle Semeria, Pierre Mur, Franck Fournel, Hubert Moriceau, Hubert Eymery, Noël Magnea, Thierry Baron, François Martin
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Publication number: 20030186512Abstract: The invention relates to a device comprising microstructures or nanostructures on a support, characterized in that the support comprises:Type: ApplicationFiled: March 28, 2003Publication date: October 2, 2003Inventors: Marie-No?euml;lle Semeria, Pierre Mur, Franck Fournel, Hubert Moriceau, J?ouml;el Eymery, N?ouml;el Magnea, Thierry Baron, Francois Martin