Patents by Inventor Pierre Parrens

Pierre Parrens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4620893
    Abstract: An apparatus for plasma treatment of plate-shaped substrates comprises a reaction vessel (2) provided with supply opening (48) and discharge opening (50) for a reaction gas. Anode (46) and a plurality of cathodes (13) are also provided. At the periphery of the cathodes (13) are provided gas flow passges (40, 41) through which the reaction gas may flow from the gas supply opening (48). The gas flow passages (40, 41) are provided on the side of surfaces (15c, 16c) of the cathodes receiving small plates. Discharge opening (50) is arranged downstream of gas flow passages (40, 41). The apparatus may also comprise a removable tray (38) to load and unload the small plates, and the flow passages (40, 41) may be delimited by the walls of the electrodes and of passages traversing the tray (38).
    Type: Grant
    Filed: February 28, 1985
    Date of Patent: November 4, 1986
    Assignee: Nextral
    Inventor: Pierre Parrens
  • Patent number: 4544445
    Abstract: The invention relates to a process for the positioning of an interconnection line on an electric contact hole in an integrated circuit. According to the invention, one or more conductive layers forming a conductive covering are deposited on the complete integrated circuit. The first conductive layer is deposited by an isotropic process. The interconnection line to be produced is then masked by a resin layer, followed by the successive etching of each conductive layer. Finally, an overetching of these conductive layers is effected in the electric contact hole, followed by the elimination of the resin.
    Type: Grant
    Filed: March 16, 1984
    Date of Patent: October 1, 1985
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre Jeuch, Jean-Pierre Lazzari, Pierre Parrens
  • Patent number: 4455193
    Abstract: Process for producing the field oxide of an integrated circuit, wherein it comprises the following successive stages:(a) producing a resin mask on a first region of a doped semiconductor substrate, in which will be formed the active component of the integrated circuit,(b) production of a first etching over a height h of a second region of the doped semiconductor substrate, in which it is wished to produce the field oxide,(c) implantation of ions in the second region of the remaining substrate, giving a doping of the same type as that of the substrate,(d) deposition of an insulating layer on the complete substrate,(e) deposition of a resin layer on the insulating layer,(f) production of a second simultaneous etching of the resin layer and the insulating layer, until the complete elimination of that region of the oxide layer positioned above the first region of the substrate in which will be produced the active component of the integrated circuit.
    Type: Grant
    Filed: June 29, 1983
    Date of Patent: June 19, 1984
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Pierre Jeuch, Pierre Parrens