Abstract: The application is for telecommunication networks of asynchronous transfer mode. The device contains a time stamp generator (TSG) for assigning a time stamp to each cell; a buffer memory (BM); an address memory (FSAM) for memorizing the address of the first sub-cell of each cell; a link memory (LM); and a circuit for indicating the address of the buffer memory that contains the first sub-cell of a cell.

Abstract: The device is for telecommunication networks with an asynchronous transfer mode and contains, in particular:a time stamp generator (TSG), for assigning a time stamp to each cell;a buffer memory (BM);an address memory (FSAM) to memorize the address of the first sub-cell of each cell;a linking memory (LM);a circuit (CU) for finding the buffer memory address containing the first sub-cell of a cell; this circuit comprises, in particular: a memory that is accessible by its content, for memorizing the waiting cell identifiers, each containing the identity of a time period during which the waiting delay of the cell expires, and of the identity of at least one output from which the cell is to be emitted; and a queuing memory for each output, where the order number is recorded each time the waiting delay of at least one cell, which must be emitted from that output, expires; each queuing memory is of the type accessible by its content, and the numbers are searched in ascending order when this output becomes available.

Abstract: To supervise a telephone subscriber line (v'2, v'1,) and provide it with adjustable AC and DC termination impedances from the exchange (v1, v2), these are supplied by an impedance synthesis multiple loop split into separate DC and AC loop parts by filters at the output of a sense amplifier in the common loop part and fed (e) through a Herter bridge. The amplifier AC output has however to be limited to avoid saturation by a larger DC signal. It now includes a Miller effect integrator output stage (A2) with a low pass frequency response supplying the DC loop and also feeding back an input stage (A1) so that the latter exhibits a high pass frequency response with a DC free output to drive the AC loop and the consequent ability to supply a larger AC output. Further circuits improve dial pulse detection (LP), reduce external capacitances (C1) and limit power consumption (PG5 and PG6).