Abstract: A low voltage positive emitter coupled logic (LV-PECL) buffer fabricated in the complimentary oxide metal silicon (CMOS) process. The LV-PECL buffer in CMOS is operable for a wide frequency range from DC to frequencies as high as 800 MHZ in 0.5 um process. Synchronized feedforward logic is utilized without the need for a feedback loop. N-MOSFET's, which are faster than P-MOSFET's, are used for the implementation of switched current sources. The switched current sources deliver a pull-up current variable in time and as a result have more than two values. The pull-up current is sharply increased in value during the output waveform transition times in an impulse manner.

Abstract: A CMOS single-ended frequency doubler with improved subharmonic rejection and low phase noise which allows a single ended reference signal to be utilized in a Balanced Colpitts oscillator. The input is reproduced with a 180-degree phase shift for the opposite Colpitts transistor. This is achieved by adding two PMOS transistors. One transistor is placed as a follower, which reproduces any voltage shift applied to its gate to its source. Another transistor is a matching transistor for balance. By applying the single-ended signal to the gate of the follower transistor, it is reproduced at the source. The rest of the circuit takes advantage of the summing of two period currents with a 180-degree phase shift. The present invention achieves superior performance for frequency doubling due to the squaring of the gate voltage in the corresponding drain current. As a result, the double frequency component is further enhanced.

Abstract: A low power balanced Colpitts oscillator circuit with improved negative resistance. The oscillator circuit comprises two cross-coupled Colpitts oscillators with a crystal oscillator connected between the two oscillators. A single current source can be used for both Colpitts oscillators since only one Colpitts needs a current source at a time. Using a single current source cuts the power consumption in half. Alternatively, a transistor in each Colpitts oscillator can act as a current source, which is turned on or off depending on the state of the Colpitts transistor. The two current sources are biased at a common level and matched to ensure the circuit remains symmetrical. An additional benefit of the present invention is that the negative resistance is directly improved.

Abstract: A CMOS-logic compliant output buffer design for clock signals which limits the output amplitude without shifting the DC cross point while preserving the duty cycle. The waveform's VOH is limited to a VOHmax value less than VDD and its VOL is limited to a VOLmin value grater than 0V. For charging, the output buffer circuit is open but the current is limited to charging the capacitive load to VOHmax which is less than VDD and the output buffer circuit is tri-stated when VOH reaches VOHmax. For discharging, the output buffer circuit is open, but the current is limited to discharging the capacitive load to VOLmin which is greater than 0V and the output buffer circuit is tri-stated when VOL reaches VOLmin. In this way, the signal amplitude and current consumption are reduced while maintaining sharp rising and falling edges as well as preserving the duty cycle.

Abstract: A telecommunication switching system including a plurality of terminal circuits each associated with a common control device. The common control device is coupled to a switching network through two interface circuits which operate asynchronously. The control device includes a processor and control means to successively allocate the processor to each of the terminal interface circuits. This uniquely simple solution requires only one control device while providing the high reliability that may be achieved through the use of two interface circuits.