Abstract: A method for thinning a first layer made of a piezoelectric material including: the implantation of ions into the first layer so as to amorphize an upper portion of the first layer, and the removal of the upper portion by a chemical-mechanical polishing step.

Abstract: A process for fabricating a component includes an operation of transferring at least one layer of one or more piezoelectric or pyroelectric or ferroelectric materials forming part of a donor substrate to a final substrate, the process comprising a prior step of joining the layer to a temporary substrate via production of a fragile separating region between the donor substrate of single-crystal piezoelectric or pyroelectric or ferroelectric material and the temporary substrate, the region comprising at least two layers of different materials in order to ensure two compounds apt to generate an interdiffusion of one or more constituent elements of at least one of the two compounds make contact, the fragile region allowing the temporary substrate to be separated.

Abstract: A process for fabricating a component includes an operation of transferring at least one layer of one or more piezoelectric or pyroelectric or ferroelectric materials forming part of a donor substrate to a final substrate, the process comprising a prior step of joining the layer to a temporary substrate via production of a fragile separating region between the donor substrate of single-crystal piezoelectric or pyroelectric or ferroelectric material and the temporary substrate, the region comprising at least two layers of different materials in order to ensure two compounds apt to generate an interdiffusion of one or more constituent elements of at least one of the two compounds make contact, the fragile region allowing the temporary substrate to be separated.

Abstract: There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon—germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon—germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

Abstract: There is provided a method for the manufacture of an integrated circuit, including a substrate and an insulating layer formed on the substrate; a first pMOS transistor formed on the insulating layer and including a channel formed in a first layer of a silicon-germanium alloy, having a first thickness and first average germanium density; a gate oxide layer having a first equivalent oxide thickness; a second pMOS transistor formed on the insulating layer and further including a channel formed in a second layer of a silicon-germanium alloy, having a second thickness which is greater than the first and a second average germanium density which is lower than the first; and a gate oxide layer having a second equivalent oxide thickness which is greater than the first.

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract: Adhesion by molecular bonding of two free surfaces of first and second substrates, for example formed by monocrystalline silicon wafers, comprises at least successively: a cleaning step of the two free surfaces with hydrofluoric acid in vapor phase to make the two free surfaces hydrophobic, a rinsing step of said free surfaces with deionized water with a time less than or equal to 30 seconds a step of bringing said free surfaces into contact.

Abstract: Adhesion by molecular bonding of two free surfaces of first and second substrates, for example formed by monocrystalline silicon wafers, comprises at least successively: a cleaning step of the two free surfaces with hydrofluoric acid in vapor phase to make the two free surfaces hydrophobic, a rinsing step of said free surfaces with deionized water with a time less than or equal to 30 seconds a step of bringing said free surfaces into contact.