Patents by Inventor Pierre Rayssac
Pierre Rayssac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10002763Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing a support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the semiconductor substrate.Type: GrantFiled: November 8, 2011Date of Patent: June 19, 2018Assignee: SoitecInventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
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Patent number: 8507361Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. In another embodiment, the method includes providing a source substrate with a weakened zone defining a nucleation layer, bonding a support substrate to the source substrate, detaching the nucleation layer and support substrate at the weakened zone by applying laser irradiation stress, depositing a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited layer and removing the support substrate and nucleation layer. The result is a semiconductor substrate that includes the layer of semiconductor material on a support or target substrate.Type: GrantFiled: January 5, 2011Date of Patent: August 13, 2013Assignee: SoitecInventors: Fabrice Letertre, Bruno Ghyselen, Pierre Rayssac, Gisèle Rayssac
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Patent number: 8252664Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.Type: GrantFiled: September 27, 2011Date of Patent: August 28, 2012Assignee: SoitecInventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
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Publication number: 20120058621Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.Type: ApplicationFiled: November 8, 2011Publication date: March 8, 2012Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
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Publication number: 20120012048Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes providing an support that includes a barrier layer thereon for preventing loss by diffusion of elements derived from dissociation of the support at epitaxial growth temperatures; providing a seed layer on the barrier layer, wherein the seed layer facilitates epitaxial growth of a single crystal III-nitride semiconductor layer thereon; epitaxially growing a nitride working layer on the thin seed layer; and removing the support to form the substrate.Type: ApplicationFiled: September 27, 2011Publication date: January 19, 2012Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
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Publication number: 20110233733Abstract: The invention relates to a release substrate produced from semiconductor materials, and which includes a first substrate release layer having a surface in contact with a connecting layer, and a second substrate release layer having a surface in contact with the connecting layer opposite the first substrate release layer so that the connecting layer is located between the first substrate release layer and second substrate release layer; and a concentrated zone of solid nanoparticles located within the connecting layer to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment while also facilitating breaking of the connecting layer by mechanical action.Type: ApplicationFiled: June 2, 2011Publication date: September 29, 2011Inventors: Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac, Takeshi Akatsu
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Patent number: 8012289Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: GrantFiled: February 25, 2009Date of Patent: September 6, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Takeshi Akatsu
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Publication number: 20110171812Abstract: The invention relates to methods for fabricating a semiconductor substrate. In one embodiment, the method includes transferring a seed layer on to a support substrate; and depositing a working layer on the seed layer to form a composite substrate. The seed layer is made of a material that accommodates thermal expansion of the support substrate and of the working layer. In another embodiment, the method includes providing a source substrate with a weakened zone defining a nucleation layer, bonding a support substrate to the source substrate, detaching the nucleation layer and support substrate at the weakened zone by applying laser irradiation stress, depositing a semiconductor material upon the nucleation layer, bonding a target substrate to the deposited layer and removing the support substrate and nucleation layer. The result is a semiconductor substrate that includes the layer of semiconductor material on a support or target substrate.Type: ApplicationFiled: January 5, 2011Publication date: July 14, 2011Inventors: Fabrice Letertre, Bruno Ghyselen, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
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Patent number: 7939428Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: GrantFiled: October 28, 2010Date of Patent: May 10, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
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Publication number: 20110039368Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving substrate and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: ApplicationFiled: October 28, 2010Publication date: February 17, 2011Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisèle Rayssac
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Patent number: 7839001Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: GrantFiled: August 5, 2009Date of Patent: November 23, 2010Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
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Patent number: 7670929Abstract: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.Type: GrantFiled: January 17, 2007Date of Patent: March 2, 2010Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Carlos Mazure, Olivier Rayssac, Pierre Rayssac, legal representative, Giséle Rayssac, legal representative
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Publication number: 20090289332Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: ApplicationFiled: August 5, 2009Publication date: November 26, 2009Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
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Patent number: 7615468Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: GrantFiled: August 17, 2007Date of Patent: November 10, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative
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Patent number: 7575988Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.Type: GrantFiled: August 1, 2007Date of Patent: August 18, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Carlos Mazure, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Olivier Rayssac
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Patent number: 7544265Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: GrantFiled: July 5, 2006Date of Patent: June 9, 2009Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Pierre Rayssac, legal representative, Gisele Rayssac, legal representative, Takeshi Akatsu, Olivier Rayssac
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Publication number: 20080014712Abstract: The invention provides methods of direct bonding substrates at least one of which includes a layer of semiconductor material that extends over its front face or in the proximity thereof. The provided methods include, prior to bonding, subjecting the bonding face of at least one substrate comprising a semiconductor material to selected heat treatment at a selected temperature and in a selected gaseous atmosphere. The bonded substrates are useful for electronic, optic, or optoelectronic applications.Type: ApplicationFiled: January 17, 2007Publication date: January 17, 2008Inventors: Konstantin Bourdelle, Carlos Mazure, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
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Publication number: 20080014714Abstract: A method of fabricating a hybrid substrate by direct bonding of donor and receiver substrates where each substrate has a respective front face and surface, with the front face of the receiver substrate having a semiconductor material near the surface, and the donor substrate including a zone of weakness that defines a layer to be transferred. The method includes preparing the substrate surfaces by exposing the surface of the receiver substrate to a temperature from about 900° C. to about 1200° C. in an inert atmosphere for at least 30 sec; directly bonding together the front faces of the prepared substrates to form a composite substrate; heat treating the composite substrate to increase bonding strength between the front surfaces of the donor and receiver substrates; and transferring the layer from the donor substrate by detaching the remainder of the donor substrate at the zone of weakness.Type: ApplicationFiled: August 1, 2007Publication date: January 17, 2008Inventors: Konstantin BOURDELLE, Carlos Mazure, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
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Publication number: 20070287273Abstract: A method for making substrates for use in optics, electronics, or opto-electronics. The method may include transferring a seed layer onto a receiving support and depositing a useful layer onto the seed layer. The thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support. Preferably, the nucleation layer and the intermediate support have substantially the same chemical composition.Type: ApplicationFiled: August 17, 2007Publication date: December 13, 2007Inventors: Alice Boussagol, Bruce Faure, Bruno Ghyselen, Fabrice Letertre, Olivier Rayssac, Pierre Rayssac, Gisele Rayssac
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Publication number: 20070077729Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: ApplicationFiled: July 5, 2006Publication date: April 5, 2007Inventors: Olivier Rayssac, Takeshi Akatsu, Pierre Rayssac, Gisele Rayssac