Patents by Inventor Pierre Tomasini
Pierre Tomasini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230420521Abstract: Silicon germanium (SiGe)/silicon containing superlattice structure and methods for forming the same are provided. Various embodiments utilize SiGe layers in a SiGe/Si superlattice structure, which include varying concentrations of germanium throughout the layer to achieve reduced dislocations or a dislocation-free superlattice. For example, in some embodiments, for each SiGe layer there is a core SiGe film with a low Ge content and two thinner SiGe layers or cladding layers positioned on opposing sides of the core SiGe film with each of the SiGe cladding layers having a higher Ge content then the core SiGe film. Various embodiments provide for SiGe layers having a germanium depth profile enabling strained SiGe superlattice deposition on Si{110} substrates.Type: ApplicationFiled: January 17, 2023Publication date: December 28, 2023Inventors: Yi-Chiau HUANG, Pierre TOMASINI, Abhishek Dube
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Patent number: 9276070Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: GrantFiled: April 10, 2014Date of Patent: March 1, 2016Assignee: SoitecInventors: Christophe Figuet, Pierre Tomasini
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Patent number: 9093269Abstract: Methods for low temperature cleaning of a semiconductor surface prior to in-situ deposition have high throughput and consume very little of the thermal budget. GeH4 deposits Ge on the surface and converts any surface oxygen to GeOx. An etchant, such as Cl2 or HCl removes Ge and any GeOx and epitaxial deposition follows. A spike in Ge concentration can be left on the substrate from diffusion into the substrate. All three steps can be conducted sequentially in-situ at temperatures lower than conventional bake steps.Type: GrantFiled: December 20, 2011Date of Patent: July 28, 2015Assignee: ASM America, Inc.Inventors: Nyles W. Cody, Shawn G. Thomas, Pierre Tomasini
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Patent number: 8975165Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.Type: GrantFiled: February 17, 2011Date of Patent: March 10, 2015Assignee: SoitecInventors: Christophe Figuet, Ed Lindow, Pierre Tomasini
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Publication number: 20140217419Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: ApplicationFiled: April 10, 2014Publication date: August 7, 2014Applicant: SoitecInventors: Christophe Figuet, Pierre Tomasini
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Patent number: 8742428Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: GrantFiled: October 24, 2012Date of Patent: June 3, 2014Assignee: SoitecInventors: Christophe Figuet, Pierre Tomasini
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Patent number: 8530340Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.Type: GrantFiled: September 9, 2009Date of Patent: September 10, 2013Assignee: ASM America, Inc.Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
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Publication number: 20130153961Abstract: Methods for low temperature cleaning of a semiconductor surface prior to in-situ deposition have high throughput and consume very little of the thermal budget. GeH4 deposits Ge on the surface and converts any surface oxygen to GeOx. An etchant, such as Cl2 or HCl removes Ge and any GeOx and epitaxial deposition follows. A spike in Ge concentration can be left on the substrate from diffusion into the substrate. All three steps can be conducted sequentially in-situ at temperatures lower than conventional bake steps.Type: ApplicationFiled: December 20, 2011Publication date: June 20, 2013Applicant: ASM AMERICA, INC.Inventors: Nyles W. Cody, Shawn G. Thomas, Pierre Tomasini
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Publication number: 20130049012Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: ApplicationFiled: October 24, 2012Publication date: February 28, 2013Applicant: SoitecInventors: Soitec, Christophe Figuet, Pierre Tomasini
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Patent number: 8329571Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: GrantFiled: February 13, 2012Date of Patent: December 11, 2012Assignee: SoitecInventors: Christophe Figuet, Pierre Tomasini
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Publication number: 20120225539Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, the layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: ApplicationFiled: February 13, 2012Publication date: September 6, 2012Applicant: SOITECInventors: Christophe Figuet, Pierre Tomasini
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Publication number: 20120211870Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.Type: ApplicationFiled: February 17, 2011Publication date: August 23, 2012Applicant: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIESInventors: Christophe Figuet, Ed Lindow, Pierre Tomasini
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Patent number: 8148252Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.Type: GrantFiled: March 2, 2011Date of Patent: April 3, 2012Assignee: S.O.I. Tec Silicon on Insulator TechnologiesInventors: Christophe Figuet, Pierre Tomasini
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Patent number: 7939447Abstract: A method for depositing a single crystalline silicon film comprises: providing a substrate disposed within a chamber; introducing to the chamber under chemical vapor deposition conditions a silicon precursor, a chlorine-containing etchant and an inhibitor source for decelerating reactions between the silicon precursor and the chlorine-containing etchant; and selectively depositing a doped crystalline Si-containing film onto the substrate.Type: GrantFiled: October 26, 2007Date of Patent: May 10, 2011Assignee: ASM America, Inc.Inventors: Matthias Bauer, Pierre Tomasini
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Patent number: 7816236Abstract: Chemical vapor deposition methods use trisilane and a halogen-containing etchant source (such as chlorine) to selectively deposit Si-containing films over selected regions of mixed substrates. Dopant sources may be intermixed with the trisilane and the etchant source to selectively deposit doped Si-containing films. The selective deposition methods are useful in a variety of applications, such as semiconductor manufacturing.Type: GrantFiled: January 30, 2006Date of Patent: October 19, 2010Assignee: ASM America Inc.Inventors: Matthias Bauer, Chantal Arena, Ronald Bertram, Pierre Tomasini, Nyles Cody, Paul Brabant, Joseph Italiano, Paul Jacobson, Keith Doran Weeks
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Patent number: 7785995Abstract: Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.Type: GrantFiled: May 9, 2006Date of Patent: August 31, 2010Assignees: ASM America, Inc., S.O.I. Tec Silicon on Insulator Technologies, S.A.Inventors: Nyles W. Cody, Chantal Arena, Pierre Tomasini, Carlos Mazure
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Patent number: 7772097Abstract: An embodiment provides a method for selectively depositing a single crystalline film. The method includes providing a substrate, which includes a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology. A silicon precursor and BCl3 are intermixed to thereby form a feed gas. The feed gas is introduced to the substrate under chemical vapor deposition conditions. A Si-containing layer is selectively deposited onto the first surface without depositing on the second surface by introducing the feed gas.Type: GrantFiled: November 5, 2007Date of Patent: August 10, 2010Assignee: ASM America, Inc.Inventors: Pierre Tomasini, Nyles Cody
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Patent number: 7759199Abstract: A semiconductor substrate having recesses filled with heteroepitaxial silicon-containing material with different portions having different impurity concentrations. Strained layers can fill recessed source/drain regions in a graded, bottom-up fashion. Layers can also line recess sidewalls with one concentration of strain-inducing impurity and fill the remainder to the recess with a lower concentration of the impurity. In the latter case, the sidewall liner can be tapered.Type: GrantFiled: September 19, 2007Date of Patent: July 20, 2010Assignee: ASM America, Inc.Inventors: Shawn Thomas, Pierre Tomasini
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Patent number: 7682947Abstract: Methods for depositing epitaxial films such as epitaxial Ge and SiGe films. During cooling from high temperature processing to lower deposition temperatures for Ge-containing layers, Si or Ge compounds are provided to the substrate. Smooth, thin, relatively defect-free Ge or SiGe layers result. Retrograded relaxed SiGe is also provided between a relaxed, high Ge-content seed layer and an overlying strained layer.Type: GrantFiled: May 30, 2007Date of Patent: March 23, 2010Assignee: ASM America, Inc.Inventors: Paul D. Brabant, Joseph P. Italiano, Chantal J. Arena, Pierre Tomasini, Ivo Raaijmakers, Matthias Bauer
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Patent number: 7666799Abstract: A relaxed silicon germanium structure comprises a silicon buffer layer produced using a chemical vapor deposition process with an operational pressure greater than approximately 1 torr. The relaxed silicon germanium structure further comprises a silicon germanium layer deposited over the silicon buffer layer. The silicon germanium layer has less than about 107 threading dislocations per square centimeter. By depositing the silicon buffer layer at a reduced deposition rate, the overlying silicon germanium layer can be provided with a “crosshatch free” surface.Type: GrantFiled: April 6, 2009Date of Patent: February 23, 2010Assignee: ASM America, Inc.Inventors: Chantal Arena, Pierre Tomasini, Nyles Cody, Matthias Bauer