Patents by Inventor Pierre Valadeau

Pierre Valadeau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11477002
    Abstract: A method and system for synchronizing computers includes a bit computing module for computing of a bit by each computer, an exchange module, a bit signal pair determination module for determining a bit signal pair including the computed bit, a bit product pair determination module for determining a bit product pair indicating which bit equal to 1 of the bit signal pair of a computer can be combined with the bit of the bit signal pair determined for the other computer in the iteration n?1, a bit remainder pair determination module for determining a bit remainder pair indicating which bit equal to 1 of the bit signal pair of a computer in the iteration n is different from the bit of the bit signal pair of the other computer in the iteration n?1, a synchronized signal determination module for determining a synchronized signal based on the bit product pair and on the bit remainder pair.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: October 18, 2022
    Assignee: Airbus Operations (S.A.S.)
    Inventors: Pierre Valadeau, Matthieu Boitrel
  • Publication number: 20210328755
    Abstract: A method and system for synchronizing computers includes a bit computing module for computing of a bit by each computer, an exchange module, a bit signal pair determination module for determining a bit signal pair including the computed bit, a bit product pair determination module for determining a bit product pair indicating which bit equal to 1 of the bit signal pair of a computer can be combined with the bit of the bit signal pair determined for the other computer in the iteration n?1, a bit remainder pair determination module for determining a bit remainder pair indicating which bit equal to 1 of the bit signal pair of a computer in the iteration n is different from the bit of the bit signal pair of the other computer in the iteration n?1, a synchronized signal determination module for determining a synchronized signal based on the bit product pair and on the bit remainder pair.
    Type: Application
    Filed: April 6, 2021
    Publication date: October 21, 2021
    Inventors: Pierre Valadeau, Matthieu Boitrel