Patents by Inventor Pierre Vekeman

Pierre Vekeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7754506
    Abstract: A method of fabricating submicron objects that includes the following steps: depositing a void layer on a support, depositing a transfer layer on the void layer, producing the objects in the transfer layer, producing a hard mask on a portion of the transfer layer to delimit a region comprising a portion of the objects, and etching the combination formed by the hard mask, the transfer layer and the void layer to eliminate the hard mask and the portion of the transfer layer in the region and to open up the portion of the void layer under the region so that the objects are suspended, the rate of etching the void layer being greater than the rate of etching the transfer layer and the hard mask.
    Type: Grant
    Filed: June 15, 2006
    Date of Patent: July 13, 2010
    Assignee: Altis Semiconductor
    Inventors: Pierre Vekeman, Sodonie Lefebvre, Thierry Hoc, Pascal Deconinck
  • Publication number: 20070031984
    Abstract: A method of fabricating submicron objects that includes the following steps: depositing a void layer on a support, depositing a transfer layer on the void layer, producing the objects in the transfer layer, producing a hard mask on a portion of the transfer layer to delimit a region comprising a portion of the objects, and etching the combination formed by the hard mask, the transfer layer and the void layer to eliminate the hard mask and the portion of the transfer layer in the region and to open up the portion of the void layer under the region so that the objects are suspended, the rate of etching the void layer being greater than the rate of etching the transfer layer and the hard mask.
    Type: Application
    Filed: June 15, 2006
    Publication date: February 8, 2007
    Inventors: Pierre Vekeman, Sodonie Lefebvre, Thierry Hoc, Pascal Deconinck
  • Patent number: 6344422
    Abstract: A boro-silicate-glass (BSG) is deposited on a silicon substrate coated with a bottom SiO2 and an overlying Si3N4 layer by LPCVD using an O3/TEB/TEOS mixture at low pressure (less than 300 mTorr), low temperature (less than 500° C.) and a TEB flow which is adjusted to have a boron concentration in the BSG layer less than 10% (in weight). The BSG material deposited that way has been found to be resistant to aggressive silicon dry etch chemistries and is easily and rapidly etched in standard BSG etchants. However, very high etch rates are obtained with a HF/ethylene glycol wet chemistry. The disclosed BSG deposition method finds a valuable application in the fabrication of the buried plate in deep trench cell capacitors because no undercuts are produced in the bottom SiO2 layer sidewall exposed in the trench during the BSG layer removal.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: February 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Bruno Borgognoni, François Leverd, Bruno Sauvage, Pierre Vekeman