Abstract: A phased array transceiver element comprises a local oscillator stage for generating beamformed in-phase and quadrature local oscillator signals, the local oscillator stage comprising a phase shifter connectable to a reference frequency source and applying a first phase shift; a primary frequency multiplier input from the phase shifter and applying a primary frequency multiplication factor; a phase-splitting arrangement input from the primary frequency multiplier and having a first output and a second output, the phase-splitting arrangement applying a second phase shift at the first output and a third phase shift at the second output; a first secondary frequency multiplier input from the first output of the phase-splitting arrangement, having an output for the in-phase local oscillator signal, and applying a secondary frequency multiplication factor; and a second secondary frequency multiplier input from the second output of the phase-splitting arrangement, having an output for the quadrature local oscillator

Abstract: An RF impedance measurement circuit includes a sensing capacitor connectable with an RF signal path; a first amplitude detector and a first frequency divider, each coupled, with the measurement circuit in operation, to the RF signal path at a first terminal of the sensing capacitor; a second amplitude detector and a second frequency divider, each coupled, with the measurement circuit in operation, to a second terminal of the sensing capacitor; and a phase detection circuit connected to an output of the first frequency divider and to an output of the second frequency divider.

Abstract: An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

Abstract: A wideband radio-frequency transceiver front-end is provided. The transceiver front-end includes an antenna port and a transmission path coupled to the antenna port comprising a power amplifier and a first matching network. The transceiver front-end further includes a reception path coupled to the antenna port comprising a low noise amplifier and a second matching network. Furthermore, the transceiver front-end includes an impedance inverter coupled in-between the antenna port and the second matching network. Moreover, the transceiver front-end includes a controller comprising switching arrangement for a gate and a drain of the power amplifier. In this context, the controller is configured to initiate a first reception mode by connecting the gate of the power amplifier to ground and by connecting the drain of the power amplifier to a supply voltage.

Abstract: A differential amplifier is provided. The differential amplifier includes a first single-ended amplifying means including at least a first terminal and a second terminal, a second single-ended amplifying means including at least a first terminal and a second terminal, a first transmission line, and a second transmission line. In this context, the first terminal of the first single-ended amplifying means is connected to the second terminal of the second single-ended amplifying means via the first transmission line. In addition to this, the first terminal of the second single-ended amplifying means is connected to the second terminal of the first single-ended amplifying means via the second transmission line.

Abstract: A wideband radio-frequency transceiver front-end is provided. The transceiver front-end includes an antenna port and a transmission path coupled to the antenna port comprising a power amplifier and a first matching network. The transceiver front-end further includes a reception path coupled to the antenna port comprising a low noise amplifier and a second matching network. Furthermore, the transceiver front-end includes an impedance inverter coupled in-between the antenna port and the second matching network. Moreover, the transceiver front-end includes a controller comprising switching arrangement for a gate and a drain of the power amplifier. In this context, the controller is configured to initiate a first reception mode by connecting the gate of the power amplifier to ground and by connecting the drain of the power amplifier to a supply voltage.

Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segme

Abstract: An RF impedance measurement circuit includes a sensing capacitor connectable with an RF signal path; a first amplitude detector and a first frequency divider, each coupled, with the measurement circuit in operation, to the RF signal path at a first terminal of the sensing capacitor; a second amplitude detector and a second frequency divider, each coupled, with the measurement circuit in operation, to a second terminal of the sensing capacitor; and a phase detection circuit connected to an output of the first frequency divider and to an output of the second frequency divider.

Abstract: An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

Abstract: A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

Abstract: A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segme

Abstract: A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.

Abstract: A device for phase shifting is disclosed, comprising an input amplifier, a biasing circuit, a first output amplifier and a second output amplifier being variable-gain amplifiers, and a quadrature hybrid coupler. The input amplifier is connected to an input port of the coupler, the first output amplifier is connected to a through port of the coupler, the second output amplifier is connected to a coupled port of the coupler, and the biasing circuit is connected to an isolated port of the coupler. The device also includes, the quadrature hybrid coupler configured to receive, at the input port, an input signal from the input amplifier, output, at the through port, a through signal, receive, at the isolated port, a bias signal from the biasing circuit, and output, at the coupled port, a coupled signal having a phase differing from a phase of the through signal.

Abstract: A device for phase shifting is disclosed, comprising an input amplifier, a biasing circuit, a first output amplifier and a second output amplifier being variable-gain amplifiers, and a quadrature hybrid coupler. The input amplifier is connected to an input port of the coupler, the first output amplifier is connected to a through port of the coupler, the second output amplifier is connected to a coupled port of the coupler, and the biasing circuit is connected to an isolated port of the coupler. The device also includes, the quadrature hybrid coupler configured to receive, at the input port, an input signal from the input amplifier, output, at the through port, a through signal, receive, at the isolated port, a bias signal from the biasing circuit, and output, at the coupled port, a coupled signal having a phase differing from a phase of the through signal.

Abstract: Simulation methods and simulators are presented which operate on a computer under software control. Said computer simulation methods and simulators are specially suited for simulating digital circuits and mixed analog digital circuits. The methods enable efficient simulation, meaning resulting in a fast simulation while still obtaining accurate results. With fast simulation is meant that the simulation can be completed in a short simulation time. Accurate means that the signals obtained or determined by simulation are good approximations of the signals that would be measured when the circuit, which representation is under simulation, is actually running in real world. Indeed the simulation methods and the related simulation apparatus or simulator exploits a representation of a circuit.

Abstract: A method for estimating the BER for telecommunication systems, particular those characterized by signals having high crest factors or causing large inband nonlinear distortions. The set of signals used by the system is divided into subsets according to a characteristic such as signal crest factor, and a BER estimation method is chosen for each subset. Signals causing a large BER are simulated more efficiently using a Monte Carlo simulation, while low BER estimations more efficiently use a quasi-analytical method. The method results in improved accuracy because the noise contribution in quasi-analytical methods can be better approximated for signals having a small crest factor range, and drastically reduces the number of experiments, measurements or simulations which are needed to obtain an accurate BER estimation, as compared to standard Monte Carlo techniques.

Abstract: A method for estimating the BER for telecommunication systems, particular those characterized by signals having high crest factors or causing large inband nonlinear distortions. The set of signals used by the system is divided into subsets according to a characteristic such as signal crest factor, and a BER estimation method is chosen for each subset. Signals causing a large BER are simulated more efficiently using a Monte Carlo simulation, while low BER estimations more efficiently use a quasi-analytical method. The method results in improved accuracy because the noise contribution in quasi-analytical methods can be better approximated for signals having a small crest factor range, and drastically reduces the number of experiments, measurements or simulations which are needed to obtain an accurate BER estimation, as compared to standard Monte Carlo techniques.