Abstract: A method for protecting a generation, by an electronic circuit, of at least one prime number by testing the prime character of successive candidate numbers, including: for each candidate number: the calculation of a reference number involving at least one first random number, and at least one primality test based on modular exponentiation calculations; and for a candidate number having successfully passed the primality test: a test of consistency between the candidate number and its reference number.

Abstract: A method and a circuit for detecting a loss in the equiprobable character of a first output bit flow originating from at least one first element of normalization of an initial bit flow, including analyzing the flow rate of the normalization element.

Abstract: A method and a circuit for extracting a secret datum from an integrated circuit taking part in an authentication procedure that uses an external device that takes this secret datum into account, the secret datum being generated on request and made ephemeral.

Abstract: A method and a circuit for protecting against possible fault injections a calculation successively performed by several hardware cells of a same electronic element, including: starting a first execution of the calculation; starting a second execution of the same calculation once the first execution has freed a first cell and goes on in a second cell; synchronizing the executions so that the second execution uses a cell only when the first execution has passed to the next cell; and verifying the identity between the two results at the end of the execution of the two calculations.

Abstract: A circuit for calculating a discriminating function with successive iterations and with a work register on data divided into blocks, including: a single operator in wired logic for executing the function; a plurality of work registers sharing the operator; and an element for selecting one of the work registers to be associated with the operator.

Abstract: The invention concerns a method and a circuit for protecting a numerical quantity (d) contained in an integrated circuit (1) on a first number of bits (n), in a modular exponentiation computing of a data (M) by said numerical quantity, which consists in: selecting at least one second number (j) included between the unit and said first number minus two; dividing said numerical quantity into at least two parts, a first part (d(j?1, 0)) comprising, from the bit of rank null, a number of bits equal to said second number, a second part (d(n?1, j)) comprising the remaining bits; for each part of the quantity, computing a first modular exponentiation (23, 33) of said data by the part concerned and a second modular exponentiation (36, 34) of the result of the first by the FIG. 2 exponentiated to the power of the rank of the first bit of the part concerned; and computing (35) the product of the results of the first and second modular exponentiations.

Abstract: A method for protecting the execution of an algorithmic calculation taking into account at least one valid piece of data and at least one secret key by an integrated circuit, and performing several iterations of an encryption calculation, including executing the algorithm with the valid data between several executions of the same algorithm with invalid data corresponding to a combination of the valid data with predetermined masks.

Abstract: A method and a circuit for standardizing a noise source providing an initial bit flow, including dividing the initial bit flow into bit words of identical lengths, and assigning an output state according to the states of the bits of the current word and to a pre-established assignment rule, the assignment rule being inverted according to the occurrence, in the initial bit flow, of words, all the bits of which have identical states.

Abstract: A method and a circuit for detecting a possible loss of the equiprobable character of a first output bit flow originating from at least one first normalization element of an initial bit flow, consisting of submitting the initial flow to at least one second normalization element of a nature different from the first one, pairing, bit to bit, the flows originating from the two elements, and checking the equidistribution of the different state pairs.

Abstract: A method for performing at least one jump in a program executed by a processor, including determining a result over several bits as an indicator that a desired condition has been complied with, the result corresponding to an operation taking into account at least one predetermined value and at least one current value; and calculating a jump address which is a function of the result.

Abstract: A method and a circuit for normalizing a noise source providing an initial bit flow, including conditioning the state of an output bit to the respective states of the bits of the initial flow examined by words of identical lengths and, upon occurrence of a word of bits of identical states, conditioning the state of the current output bit to the state of at least one previous output bit.

Abstract: A method for verifying the integrity of a key implemented in a symmetrical ciphering or deciphering algorithm, including the steps of complementing to one at least the key; and verifying the coherence between two executions of the algorithm, respectively with the key and with the key complemented to one.

Abstract: A method for protecting an integrated circuit, including at least one non-volatile memory, including the steps of detecting a possible disturbance in the flow of a program executed by the integrated circuit, modifying the value of a digital variable in a volatile storage element in case of a disturbance detection and, in a way independent in time from the detection, intervening upon the non-volatile memory according to the value of said variable.

Abstract: A method and a circuit for normalizing an initial bit flow, provided by a noise source, comprising dividing the bit flow into words of identical lengths, and assigning to each bit word of the initial flow an output state, the occurrence of a word, all the bits of which have identical states, alternately resulting in the assignment of a first state or of a second one.

Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).

Abstract: A method and a circuit for ciphering or deciphering data with a key by using at least one variable stored in a storage element and updated by the successive operations, the variable being masked by at least one first random mask applied before use of the key, then unmasked by at least one second mask applied after use of the key, at least one of the masks being dividable into several portions successively applied to the variable and which, when combined, represent the other mask.

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

Abstract: A method and a system for blocking an integrated circuit after detection of an attempt of unauthorized access to information that it contains, in which a first program of generation of a second program to be executed in a random access memory of the integrated circuit is executed, the second program including several instruction sequences and each sequence ending with a branching to another sequence; and the second program is executed.

Abstract: A method for controlling the execution of at least one program in an electronic circuit and a processor for executing a program, in which at least one volatile memory area of the circuit is, prior to the execution of the program to be controlled, filled with first instructions resulting in an exception processing; the program contains instructions for replacing all or part of the first instructions with second valid instructions; and the area is called for execution of all or part of the instruction that it contains at the end of the execution of the instruction program.

Abstract: A method of cyphering and/or decyphering, by an integrated circuit, of a digital input code by means of several keys, comprising: dividing the code into several data blocks of same dimensions; and applying to said blocks several turns of a cyphering or decyphering comprising submitting each block to at least one same non-linear transformation and of subsequently combining each block with a different key at each turn, the operands being masked, upon execution of the method, by at least one first random number having the size of the code and all the blocks of which have the same value by combining, by an XOR-type function, the input and output blocks of the non-linear transformation with said random number.