Abstract: For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model description allowing for simulating the dynamic response behaviour at an output of the victim net with respect to an input signal of the victim net and/or of the at least one aggressor net. A characteristic property of the response behaviour at the output of the victim net is represented as an output function of the simulation, the value of the output function depending on input parameters of the simulation. The output function is evaluated as to find an extremum of the output function in a preset range of the input parameters.

Abstract: A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock delay of a clock signal, which causes storage of a data item on the data path, taking into account a check. The check is determined dependent on a data slew of a signal on the data path and a clock slew of the clock signal in such a way that a positive time difference ensures the correct saving of the data item.

Abstract: For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model description allowing for simulating the dynamic response behaviour at an output of the victim net with respect to an input signal of the victim net and/or of the at least one aggressor net. A characteristic property of the response behaviour at the output of the victim net is represented as an output function of the simulation, the value of the output function depending on input parameters of the simulation. The output function is evaluated as to find an extremum of the output function in a preset range of the input parameters.

Abstract: A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock delay of a clock signal, which causes storage of a data item on the data path, taking into account a check. The check is determined dependent on a data slew of a signal on the data path and a clock slew of the clock signal in such a way that a positive time difference ensures the correct saving of the data item.

Abstract: A method and apparatus for verifying an integrated circuit design composed of both synchronous and asynchronous regions. The computer implemented system imports a design combining synchronous and asynchronous regions and utilizes a static timing analyzer to automatically determine the boundaries of the asynchronous regions including input and output probe points at the inputs and outputs of the asynchronous regions. The static timing analyzer also generates a netlist of the asynchronous regions as well as certain information indicative of the signal arrival times of data sensed over the input probe points of the asynchronous regions. A functional simulator then uses test vectors generated for the primary inputs of the integrated circuit design and automatically determines a set of test vectors specifically for the asynchronous portion by monitoring the input probe points. This can be done for each asynchronous region.

Abstract: A linear feedback shift register has two alternatively selectable feedback configurations enabling the shift register to produce either a pseudo-random state sequence or the reverse of that sequence. The shift register configuration may be characterized by a set of simple parameters and the register is thereby suitable for automatic synthesis.