Patents by Inventor Piers Tremlett
Piers Tremlett has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071851Abstract: An electronic device package includes a frame, an electronic device mounted to the frame, surface-mount leads, and a gel at least partially filling a cavity between the electronic device and the frame. The electronic device includes electronic circuitry provided on an electronic device substrate, and the surface-mount leads are electrically connected to the electronic circuitry and extend laterally and outwardly from an outer perimeter of the frame. The gel in the cavity covers the electronic circuitry.Type: ApplicationFiled: October 10, 2022Publication date: February 29, 2024Applicant: Microchip Technology Caldicot LimitedInventors: Piers Tremlett, Dan Chenery, Stylianos Syrigos
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Publication number: 20230326834Abstract: An apparatus includes a busbar and a heat-generating electronic device mounted on a first side of the busbar, the heat-generating electronic device being electrically and thermally coupled to the first side of the busbar. The busbar includes an array of non-planar physical structures on a second side of the busbar opposite the first side of the busbar. The apparatus includes a dielectric coating on the array of non-planar physical structures, the dielectric coating defining a non-planar dielectric surface on the second side of the busbar.Type: ApplicationFiled: October 31, 2022Publication date: October 12, 2023Applicant: Microchip Technology Caldicot LimitedInventors: Piers Tremlett, George Taylor
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Patent number: 9698124Abstract: An embedded integrated circuit package is made by providing a substrate with a patterned conductor layer defining bond pads. One or more components typically with upwardly facing contact pads are mounted on the substrate. The contact pads are wire bonded to the bond pads of the patterned conductor layer. A series of layers, each with one or more cut-outs corresponding to locations of the components forms a first solid stack containing cavities accommodating the components and associated wires. In one embodiment the layers are fiberglass layers and the layers are cured in the presence of a resin to form a solid body. In another embodiment the layers are thermoplastic layers.Type: GrantFiled: February 29, 2016Date of Patent: July 4, 2017Assignee: Microsemi Semiconductor LimitedInventors: Piers Tremlett, Richard Birch
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Publication number: 20160260685Abstract: An embedded integrated circuit package is made by providing a substrate with a patterned conductor layer defining bond pads. One or more components typically with upwardly facing contact pads are mounted on the substrate. The contact pads are wire bonded to the bond pads of the patterned conductor layer. A series of layers, each with one or more cut-outs corresponding to locations of the components forms a first solid stack containing cavities accommodating the components and associated wires. In one embodiment the layers are fiberglass layers and the layers are cured in the presence of a resin to form a solid body. In another embodiment the layers are thermoplastic layers.Type: ApplicationFiled: February 29, 2016Publication date: September 8, 2016Inventors: Piers Tremlett, Richard Birch
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Patent number: 8829684Abstract: An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive pathways and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.Type: GrantFiled: November 20, 2013Date of Patent: September 9, 2014Assignee: Microsemi Semiconductor LimitedInventors: Piers Tremlett, Michael Anthony Higgins, Martin McHugh
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Publication number: 20140070421Abstract: An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive backside. Conductive pathways extend between the front and back sides of the integrated circuit. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive pathways and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.Type: ApplicationFiled: November 20, 2013Publication date: March 13, 2014Applicant: MICROSEMI SEMICONDUCTOR LIMITEDInventors: Piers Tremlett, Michael Anthony Higgins, Martin McHugh
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Patent number: 8643192Abstract: An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive back side. Conductive vias extend through the integrated circuit between the front and back sides. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive vias and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.Type: GrantFiled: May 16, 2012Date of Patent: February 4, 2014Assignee: Microsemi Semiconductor LimitedInventors: Piers Tremlett, Michael Anthony Higgins, Martin McHugh
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Publication number: 20120292781Abstract: An integrated circuit package has a host integrated circuit with an active front side that is surface-mounted on a support and an inactive back side. Conductive vias extend through the integrated circuit between the front and back sides. A redistribution layer on the back side of the host integrated circuit provides conductive traces and contact pads. The traces of the redistribution layer establish connection between the conductive vias and the contact pads. At least one additional component is surface-mounted on the back side of the host integrated circuit by electrical connection to the contact pads of the redistribution layer to provide a compact three-dimensional structure. In an alternative embodiment, the additional components can be mounted on the active side.Type: ApplicationFiled: May 16, 2012Publication date: November 22, 2012Applicant: MICROSEMI SEMICONDUCTOR LIMITEDInventors: Piers Tremlett, Michael Anthony Higgins, Martin McHugh