Patents by Inventor Piet De Moor

Piet De Moor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11012628
    Abstract: A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: May 18, 2021
    Assignee: IMEC VZW
    Inventors: Maarten Rosmeulen, Pierre Boulenc, Piet De Moor
  • Patent number: 10742916
    Abstract: An imaging sensor is disclosed, comprising: a set of at least two charge-coupled device, CCD, sub-arrays, wherein each sub-array comprises pixels arranged in columns and rows, and each pixel being arranged to accumulate an electric charge proportional to an intensity of light incident on the pixel; a time delay and integration, TDI, clocking circuitry for controlling and timing transfer of accumulated electric charges between rows of pixels in a column direction in order to integrate the accumulated electric charges in each column of pixels; wherein each CCD sub-array further comprises a readout row for converting the integrated electric charge of each column of pixels into voltage or current, wherein the readout row comprises transistors enabling readout of the signal by the readout block; and a readout block which is arranged to receive input from selected readout rows and convert the input into digital domain or convert the input to a combined representation of pixel values based on the set of CCD sub-arra
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 11, 2020
    Assignee: IMEC VZW
    Inventors: Jonathan Borremans, Nicolaas Tack, Maarten Rosmeulen, Paul Goetschalckx, Piet De Moor
  • Publication number: 20200145586
    Abstract: A device for time delay and integration imaging comprises: an array of pixels being arranged in rows and columns extending in a first and second direction, respectively. Pixels may accumulate generated charges in response to received electro-magnetic radiation along each column. The rows comprise at least one lateral charge shifting row to selectively shift accumulated charges in a column to an adjacent column and a controller configured to receive at least two angle correction input values. Each angle correction input value is based on a received intensity of electro-magnetic radiation on a measurement line, wherein the at least two angle correction input values are acquired by measurement lines extending in directions defining different angles in relation to the second direction, wherein the controller is configured to, based on the received at least two angle correction input values, control activation of the at least one lateral charge shifting row.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 7, 2020
    Inventors: Maarten Rosmeulen, Pierre Boulenc, Piet De Moor
  • Publication number: 20190132541
    Abstract: An imaging sensor is disclosed, comprising: a set of at least two charge-coupled device, CCD, sub-arrays, wherein each sub-array comprises pixels arranged in columns and rows, and each pixel being arranged to accumulate an electric charge proportional to an intensity of light incident on the pixel; a time delay and integration, TDI, clocking circuitry for controlling and timing transfer of accumulated electric charges between rows of pixels in a column direction in order to integrate the accumulated electric charges in each column of pixels; wherein each CCD sub-array further comprises a readout row for converting the integrated electric charge of each column of pixels into voltage or current, wherein the readout row comprises transistors enabling readout of the signal by the readout block; and a readout block which is arranged to receive input from selected readout rows and convert the input into digital domain or convert the input to a combined representation of pixel values based on the set of CCD sub-arra
    Type: Application
    Filed: April 6, 2017
    Publication date: May 2, 2019
    Inventors: Jonathan BORREMANS, Nicolaas TACK, Maarten ROSMEULEN, Paul GOETSCHALCKX, Piet De Moor
  • Publication number: 20100264538
    Abstract: A method for the fabrication of electrical interconnects in a substrate is disclosed. In one aspect, the method includes providing a substrate having a first main surface. The method may further include producing a ring structure in the substrate from the first main surface, which surrounds an inner pillar structure and has a bottom surface. The method may further include filling the ring structure with a dielectric material. The method may further include providing a conductive inner pillar structure, thereby forming an interconnect structure, which forms an electrical path from the bottom surface up until the first main surface. This conductive inner pillar structure can for example be provided by removing the inner pillar structure leaving a pillar vacancy and partially filling the vacancy with a conductive material. The dielectric material may be applied in liquid phase.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 21, 2010
    Applicant: IMEC
    Inventors: Bart Swinnen, Philippe Soussan, Deniz Sabuncuoglu Tezcan, Piet De Moor
  • Publication number: 20070040281
    Abstract: To provide a semiconductor device configured that a micro device having a device substrate, a function element provided on the device substrate and having an oscillator or a movable part, first lands provided on a surface of the device substrate by being arranged on its outer circumference portion of the function element, and bumps provided to the first lands is mounted on the circuit board having second lands formed to correspond to the bumps, from the bump formation surface side, so that the bumps and the second lands are electrically connected; on which a sealing resin layer is formed to go round the outer circumference portion of the function element to fix connection portions of the bumps and the second lands, and to seal a clearance between the device substrate and the circuit board; and a cavity portion is formed between the function element and the circuit board.
    Type: Application
    Filed: August 18, 2006
    Publication date: February 22, 2007
    Inventors: Hirokazu Nakayama, Akihiko Okubora, Yoichi Oya, Hirohito Miyazaki, Kris Baert, Ingrid De Wolf, Piet De Moor, Eric Beyne
  • Patent number: 6740542
    Abstract: The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: May 25, 2004
    Assignees: Interuniversitair Microelektronica Centrum, Eastman Kodak Company
    Inventors: Ann Witvrouw, Atze de Vries, Piet De Moor, Luc Haspeslagh, Brigitte Parmentier, Agnes Verbist, Constantine Anagnostopoulos
  • Patent number: 6707121
    Abstract: Structures and methods are disclosed to produce mechanical strength in Micro Electro Mechanical Systems by increasing the moment of inertia of some of the composing elements. In one aspect, a thermal sensor with improved mechanical strength, thermal insulation and time constant is achieved. Moreover, the current method and apparatus is advantageous in terms of process time and process cost, particularly in the area of lithographic patterning.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: March 16, 2004
    Assignee: Interuniversitair Microelektronica Centrum (IMEC VZW)
    Inventors: Piet De Moor, Chris Van Hoof
  • Publication number: 20020108926
    Abstract: The present invention is related to a method for producing micromachined devices for use in Microelectromechanical Systems (MEMS), comprising the steps of providing a crystalline wafer, and processing from said wafer at least one micromachined device comprising at least one elongated opening and/or cavity, having a longitudinal axis, so that said longitudinal axis is at an angle to a direction which lies along the intersection of the front plane of the wafer and a cleavage plane, said cleavage plane being defined as a plane along which cleavage of the wafer is most likely to occur.
    Type: Application
    Filed: October 9, 2001
    Publication date: August 15, 2002
    Inventors: Ann Witvrouw, Atze de Vries, Piet De Moor, Luc Haspeslagh, Brigitte Parmentier, Agnes Verbist, Constantine Anagnostopoulos
  • Publication number: 20020009821
    Abstract: Structures and methods are disclosed to produce mechanical strength in Micro Electro Mechanical Systems by increasing the moment of inertia of some of the composing elements. In one aspect, a thermal sensor with improved mechanical strength, thermal insulation and time constant is achieved. Moreover, the current method and apparatus is advantageous in terms of process time and process cost, particularly in the area of lithographic patterning.
    Type: Application
    Filed: March 23, 2001
    Publication date: January 24, 2002
    Inventors: Piet De Moor, Chris Van Hoof