Patents by Inventor Piet WESSELS

Piet WESSELS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9105687
    Abstract: A method of manufacturing a semiconductor device includes forming a trench that includes a needle defect, depositing a high density plasma oxide over the trench including the needle defect, removing the part of the high density oxide and the liner oxide over the needle defect by applying an oxide etch, and after the step of applying the oxide etch, etching back the needle defect by applying a polysilicon etch.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: August 11, 2015
    Assignee: NXP B.V.
    Inventors: Jerome Dubois, Piet Wessels, Gaurav Singh Bisht, Jayaraj Thillaigovindan, Eric Ooms, Naveen Agrawal
  • Patent number: 8957500
    Abstract: A high-voltage metal capacitor with easy integration into existing semiconductor manufacturing processes can provide isolation capacitors up to several kilovolts. The capacitor includes a support layer with internal structure, including a lower place, a bond pad on the support layer, an upper plate disposed on the support layer, the upper plate being arranged above the lower plate, a dielectric layer, at least part of which is between the lower and upper plates, and a passivation layer, at least part of which covers at least part of the upper plate and part of the dielectric layer. A first opening extends from the surface through the passivation and dielectric layers to the lower plate, and a second opening extends from the surface through the passivation layer to the upper plate. A method of manufacturing the capacitor.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Jerôme Guillaume Anna Dubois, Piet Wessels
  • Patent number: 8847347
    Abstract: Disclosed is an integrated circuit die comprising an active substrate including a plurality of components laterally separated from each other by respective isolation structures, at least some of the isolation structures carrying a further component, wherein the respective portions of the active substrate underneath the isolation structures carrying said further components are electrically insulated from said components. A method of manufacturing such an IC die is also disclosed.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: September 30, 2014
    Assignee: NXP B.V.
    Inventors: Piet Wessels, Nico Berckmans, Khin Hoong Lim, Michael John Ben Bolt, Jerome Guillaume Anna Dubois, Naveen Agrawal, Gaurav Singh Bisht, Jayaraj Thillaigovindan, Jie Liao
  • Publication number: 20140097516
    Abstract: A high-voltage metal capacitor with easy integration into existing semiconductor manufacturing processes can provide isolation capacitors up to several kilovolts. The capacitor includes a support layer with internal structure, including a lower place, a bond pad on the support layer, an upper plate disposed on the support layer, the upper plate being arranged above the lower plate, a dielectric layer, at least part of which is between the lower and upper plates, and a passivation layer, at least part of which covers at least part of the upper plate and part of the dielectric layer. A first opening extends from the surface through the passivation and dielectric layers to the lower plate, and a second opening extends from the surface through the passivation layer to the upper plate. A method of manufacturing the capacitor.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Inventors: Jerôme Guillaume Anna DUBOIS, Piet WESSELS