Patents by Inventor Pieter J. Van Der Zaag
Pieter J. Van Der Zaag has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230372025Abstract: An intravascular therapy guidance system includes a processor circuit in communication with an extravascular imaging device. The processor circuit receives, from the extravascular imaging device, an extravascular image stream. The processor circuit determines a therapy region of a blood vessel in the extravascular image stream and outputs a screen display to a display in communication with processor circuit. The screen display includes the extravascular image stream of the blood vessel including movement of an intravascular therapy device within the blood vessel to deliver an intravascular therapy to the therapy region and a graphical representation of the therapy region overlaid on the extravascular image stream.Type: ApplicationFiled: September 28, 2021Publication date: November 23, 2023Inventors: Pieter J. VAN DER ZAAG, John Arthur PEDERSEN
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Patent number: 7524688Abstract: An active plate (2) for an active matrix display device (16), the active plate (2) comprising a substrate (4), a pixel area (6) and an adjacent drive circuit area (8). Both areas include polycrystalline silicon material formed by a process in which a metal is used to enhance the crystallization process (MIC poly-Si), but only the MIC poly-Si in the drive circuit area (8) is subjected to an irradiation process using an energy beam (10). TFTs are fabricated with MIC poly-Si which have leakage currents in the off state sufficiently low for them to be acceptable for use as switching elements in the pixel area of matrix display devices. As only the drive circuit area (8) need be irradiated to provide poly-Si having the desired mobility, the time taken by the irradiation process can be significantly reduced.Type: GrantFiled: May 15, 2003Date of Patent: April 28, 2009Assignee: TPO Hong Kong Holding LimitedInventors: Pieter J. Van Der Zaag, Soo Y. Yoon, Nigel D. Young
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Patent number: 7187422Abstract: A method for use in the fabrication of active plates for pixellated devices, such as active matrix liquid crystal displays, having pixel electrodes (38) and associated address lines (32) formed from a layer of transparent conductive material (53) through which the conductivity of the address lines is improved. The transparent conductive layer (53) and a metal layer (54) are deposited in succession and followed by a shielding layer (60), e.g. of photoresist, which is patterned into a configuration of regions (67,68,69) corresponding to the required pixel dielectrodes and address lines with a property of the layer at these respective regions being different. This enables the regions of this layer corresponding to the pixel electrodes to be selectively etched away, thereby allowing the metal at these regions to be selectively removed while leaving metal at the address lines. The method simplifies the production of low mask mount TFT active plates with improved address line conductivity.Type: GrantFiled: May 25, 2004Date of Patent: March 6, 2007Assignee: Koninklijke Philips Electronics N.V.Inventors: Ian D. French, Pieter J. Van der Zaag
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Patent number: 7098493Abstract: Magnetoresistive random access memory (MRAM) is used to provide in-pixel memory circuits for display devices. A memory circuit (25) comprises memory elements, for storing a drive setting, and a read-out circuit, for example a flip-flop circuit (64), for reading-out the stored drive setting. The memory elements comprise two MRAMs (60, 62), each coupled to a respective input of the flip-flop circuit (64). A drive circuit (26) is coupled to the read-out circuit and a pixel display electrode (27) for driving the pixel display electrode (27) dependent upon the read-out drive setting with drive current that does not pass through the MRAMs (60, 62). A display device (1) is provided comprising a plurality of pixels (20) each associated with one such memory circuit (25) and drive circuit (26).Type: GrantFiled: June 4, 2003Date of Patent: August 29, 2006Assignee: Koninklijke Philips Electronics N.V.Inventors: Pieter J. Van Der Zaag, Martin J. Edwards, Kars-Michiel H. Lenssen
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Patent number: 6885425Abstract: A method of increasing the conductivity of a transparent conductive layer, in which a photoresist layer which patterns the transparent layer is given tapered edges and is partially etched. The partial etching exposing the edge regions of the underlying transparent conductor layer, which are the selectively plated. This method has a single patterning stage of the transparent layer, but uses partial etching of a tapered resist layer in order to expose a small edge region of the transparent layer for coating with a conductive layer (which can be opaque).Type: GrantFiled: October 7, 2002Date of Patent: April 26, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Ian D. French, Pieter J. Van der Zaag, Eric A. Meulenkamp
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Patent number: 6822702Abstract: A method of forming an active plate for a liquid crystal display is disclosed in which the source and drain conductors (28, 30), pixel electrodes (38) and column conductors (32) are formed by depositing and patterning a transparent conductor layer. There is selective plating of areas (52; 60) of the transparent conductor layer to form a metallic layer for reducing the resistivity of the transparent conductor layer. The plated areas include the column conductors (32) but exclude the source and drain conductors and the pixel electrodes. This enables the column conductors to be treated to reduce the resistivity, but without altering the channel length of the transistor because the source and drain parts of the layer are shielded from the plating process.Type: GrantFiled: November 29, 2001Date of Patent: November 23, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Jeffrey A. Chapman, Pieter J. Van Der Zaag, Steven C. Deane, Ian D. French
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Publication number: 20040219787Abstract: A method for use in the fabrication of active plates for pixellated devices, such as active matrix liquid crystal displays, having pixel electrodes (38) and associated address lines (32) formed from a layer of transparent conductive material (53) through which the conductivity of the address lines is improved. The transparent conductive layer (53) and a metal layer (54) are deposited in succession and followed by a shielding layer (60), e.g. of photoresist, which is patterned into a configuration of regions (67,68,69) corresponding to the required pixel dielectrodes and address lines with a property of the layer at these respective regions being different. This enables the regions of this layer corresponding to the pixel electrodes to be selectively etched away, thereby allowing the metal at these regions to be selectively removed while leaving metal at the address lines.Type: ApplicationFiled: May 25, 2004Publication date: November 4, 2004Inventors: Ian D. French, Pieter J. Van der Zaag
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Patent number: 6773941Abstract: A method for use in the fabrication of active plates for pixilated devices, such as active matrix liquid crystal displays, having pixel electrodes (38) and associated address lines (32) formed from a layer of transparent conductive material (53) through which the conductivity of the address lines is improved. The transparent conductive layer (53) and a metal layer (54) are deposited in succession and followed by a shielding layer (60), e.g. of photoresist, which is patterned into a configuration of regions (67,68,69) corresponding to the required pixel dielectrodes and address lines with a property of the layer at these respective regions being different. This enables the regions of this layer corresponding to the pixel electrodes to be selectively etched away, thereby allowing the metal at these regions to be selectively removed while leaving metal at the address lines. The method simplifies the production of low mask mount TFT active plates with improved address line conductivity.Type: GrantFiled: January 22, 2002Date of Patent: August 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Ian D. French, Pieter J. Van der Zaag
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Patent number: 6750131Abstract: A method of improving the electrical conductivity of transparent conducting lines (32) carried on a substrate (46), particularly address lines on the active plate for a pixellated device such as an active matrix liquid crystal display or the like fabricated using a low mask count process, involves forming the lines on the substrate from a deposited layer of transparent conducting material (53), e.g. ITO, and provided on their upper surface with a covering layer (72′) extending from at least one end (75) and partially covering the surface, and then performing an electroplating operation to plate the lines (80) with a plating potential being applied at that end. The covering layer (72′) assists in achieving a more uniform plated layer (80) along the length of the line. The covering layer preferably comprises photoresist defined by selective patterning and partial etching of a deposited photoresist layer (54) used for patterning the transparent layer (53).Type: GrantFiled: January 22, 2002Date of Patent: June 15, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Ian D. French, Pieter J. Van der Zaag, Daan L. De Kubber
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Patent number: 6746904Abstract: The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).Type: GrantFiled: September 3, 2003Date of Patent: June 8, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Pieter J. Van der Zaag, Steven C. Deane, Stephen J. Battersby
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Publication number: 20040048423Abstract: The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).Type: ApplicationFiled: September 3, 2003Publication date: March 11, 2004Inventors: Pieter J. Van der Zaag, Steven C. Deane, Stephen J. Battersby
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Patent number: 6566714Abstract: Short channel thin film transistors suffer from unacceptably high leakage currents. The invention provides an electronic device including a thin film transistor in which the length (20) of the channel of the transistor is 1 &mgr;m or less, and the mobility of the semiconductor material in the channel is less than 0.2 cm2/Vs. The selection of a low mobility semiconductor material results in acceptable off-current characteristics and its effect on the switching speed of the device is compensated for by the short channel length (20) of the device.Type: GrantFiled: May 9, 2002Date of Patent: May 20, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Steven C. Deane, Pieter J. Van der Zaag, Stephen J. Battersby
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Publication number: 20030034525Abstract: A method of increasing the conductivity of a transparent conductive layer, in which a photoresist layer which patterns the transparent layer is given tapered edges and is partially etched. The partial etching exposing the edge regions of the underlying transparent conductor layer, which are the selectively plated. This method has a single patterning stage of the transparent layer, but uses partial etching of a tapered resist layer in order to expose a small edge region of the transparent layer for coating with a conductive layer (which can be opaque).Type: ApplicationFiled: October 7, 2002Publication date: February 20, 2003Applicant: Koniklijke Philips Electronics N.V.Inventors: Ian D. French, Pieter J. Van Der Zaag, Eric A. Meulenkamp
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Patent number: 6498087Abstract: A method of increasing the conductivity of a transparent conductive layer, in which a photoresist layer which patterns the transparent layer is given tapered edges and is partially etched. The partial etching exposing the edge regions of the underlying transparent conductor layer, which are the selectively plated. This method has a single patterning stage of the transparent layer, but uses partial etching of a tapered resist layer in order to expose a small edge region of the transparent layer for coating with a conductive layer (which can be opaque).Type: GrantFiled: November 29, 2001Date of Patent: December 24, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: Ian D. French, Pieter J. Van Der Zaag, Eric A. Meulenkamp
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Patent number: 6494108Abstract: A magnetostrictive stress sensor is provided with a soft-ferromagnetic body having a grain structure, at least a part of the grains having a grain size in the transition region between the one-domain and the two-domain state. At this grain size, which is of the order of 1 to 9 &mgr;m for a ferrite body, a relatively large magnetostrictive effect occurs. In a practical embodiment, the ferromagnetic body is formed by a ferrite core, in particular a ferrite ring, around at least a part of which an electric oil is wound, which is incorporated in a measuring circuit for measuring changes in the self-induction of the coil under the influence of mechanical pressure exerted on the ferrite core.Type: GrantFiled: March 3, 1999Date of Patent: December 17, 2002Inventors: Pieter J. Van Der Zaag, Gerardus H. J. Somers
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Patent number: 6486662Abstract: A magnetic field sensor comprises a transducer element, which: transducer element is a Spin Tunnel Junction, comprising a first and second magnetic layer which are sandwiched about an interposed electrical insulator layer; the sensor comprises a yoke having two arms; and the first magnetic layer is in direct contact with a first portion of a first arm of the yoke.Type: GrantFiled: October 26, 1998Date of Patent: November 26, 2002Assignee: Koninklijke Philips Electronics N.V.Inventors: Jacobus J. M. Ruigrok, Reinder Coehoorn, Pieter J. Van Der Zaag
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Publication number: 20020168804Abstract: The invention provides a method of manufacturing an electronic device including a vertical thin film transistor. A layer (8) of semiconductor material is provided over an insulated gate electrode (2). A negative resist (14) is used to define source and drain electrodes (26,28) which extend over the insulating layer (8) up to the step formed therein adjacent an edge (16A) of the gate electrode (2).Type: ApplicationFiled: May 9, 2002Publication date: November 14, 2002Applicant: KONINKLIJKE PHILIPS ELECTRONIC N.V.Inventors: Pieter J. Van der Zaag, Steven C. Deane, Stephen J. Battersby
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Publication number: 20020167051Abstract: Short channel thin film transistors suffer from unacceptably high leakage currents. The invention provides an electronic device including a thin film transistor in which the length (20) of the channel of the transistor is 1 &mgr;m or less, and the mobility of the semiconductor material in the channel is less than 0.2 cm2/Vs. The selection of a low mobility semiconductor material results in acceptable off-current characteristics and its effect on the switching speed of the device is compensated for by the short channel length (20) of the device.Type: ApplicationFiled: May 9, 2002Publication date: November 14, 2002Applicant: KONINKLIJKE PHILIPS ELECTRONIC N.V.Inventors: Steven C. Deane, Pieter J. Van der Zaag, Stephen J. Battersby
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Publication number: 20020109798Abstract: A method of forming an active plate for a liquid crystal display is disclosed in which the source and drain conductors (28, 30), pixel electrodes (38) and column conductors (32) are formed by depositing and patterning a transparent conductor layer. There is selective plating of areas (52; 60) of the transparent conductor layer to form a metallic layer for reducing the resistivity of the transparent conductor layer. The plated areas include the column conductors (32) but exclude the source and drain conductors and the pixel electrodes. This enables the column conductors to be treated to reduce the resistivity, but without altering the channel length of the transistor because the source and drain parts of the layer are shielded from the plating process.Type: ApplicationFiled: November 29, 2001Publication date: August 15, 2002Inventors: Jeffrey A. Chapman, Pieter J. Van Der Zaag, Steven C. Deane, Ian D. French
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Publication number: 20020109800Abstract: A method of improving the electrical conductivity of transparent conducting lines (32) carried on a substrate (46), particularly address lines on the active plate for a pixellated device such as an active matrix liquid crystal display or the like fabricated using a low mask count process, involves forming the lines on the substrate from a deposited layer of transparent conducting material (53), e.g. ITO, and provided on their upper surface with a covering layer (72′) extending from at least one end (75) and partially covering the surface, and then performing an electroplating operation to plate the lines (80) with a plating potential being applied at that end. The covering layer (72′) assists in achieving a more uniform plated layer (80) along the length of the line. The covering layer preferably comprises photoresist defined by selective patterning and partial etching of a deposited photoresist layer (54) used for patterning the transparent layer (53).Type: ApplicationFiled: January 22, 2002Publication date: August 15, 2002Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Ian D. French, Pieter J. Van der Zaag, Daan L. De Kubber