Patents by Inventor Pieter J. W. Jochems

Pieter J. W. Jochems has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4724221
    Abstract: A method of manufacturing a semiconductor device having an integrated circuit in an epitaxial layer on a substrate in which the epitaxial layer comprises islands of conductivity type opposite to that of the substrate which are surrounded laterally by a surrounding region of the same conductivity type as the substrate, is disclosed. Both the islands and the surrounding region are formed by diffusion from buried layers through the epitaxial layer. A bipolar transistor is provided in at least one island. The p-n junctions between the islands and the surrounding region are substantially at right angles to the surface. The invention involves a method of manufacturing the device and is of particular importance for realizing very compact and fast circuits with low dissipation consisting of a combination of CMOS bipolar subcircuits.
    Type: Grant
    Filed: July 7, 1986
    Date of Patent: February 9, 1988
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4535529
    Abstract: A method of manufacturing a semiconductor device is provided in which semiconductor circuit elements are provided in regions formed by diffusion from one or more buried layers into an epitaxial layer. The diffusion is carried out such that a surface layer having substantially the same doping as the original epitaxial layer is left above the diffused into epitaxial layer above the buried layer. The surface layer serves as a reference doping for insulated gate field effect transistors to be formed. This is of a particular importance for threshold voltage determinations in CMOS circuits having adjoining "twin tub" regions diffused from buried layers of opposite conductivity types.
    Type: Grant
    Filed: July 2, 1984
    Date of Patent: August 20, 1985
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4466171
    Abstract: A method of manufacturing a semiconductor device having two juxtaposed regions (12, 16) of opposite conductivity types which adjoin a surface and which together constitute a p-n junction (9) which is preferably perpendicular to the surface and the doping concentration of which decreases towards the surface. According to the invention n-type and p-type buried layers (2, 6) are provided beside each other on a semiconductor substrate (1) and on said layers a high-ohmic epitaxial layer (7) is grown. By heating, the dopants diffuse from the buried layers through the whole thickness of the epitaxial layer and into the substrate. With suitably chosen donor and acceptor atoms (for example boron and phosphorus in silicon) n and p-type regions (12, 16) are formed in the epitaxial layer and form a p-n junction (9) perpendicular to the surface by compensation of the lateral diffusions from the buried layers.
    Type: Grant
    Filed: April 24, 1981
    Date of Patent: August 21, 1984
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4374454
    Abstract: A method is disclosed for providing in a self-registering manner underpasses in a semiconductor device having insulated gate field effect transistors, in which the underpasses below the field oxide connect electrode zones of the field effect transistors together. A first part of field oxide is obtained by local oxidation by means of an oxidation mask. After a first oxidation treatment, a part of the oxidation mask is removed and the semiconductor body is doped locally with As or Sb atoms for the underpasses. The aperture in the doping mask coincides substantially with the part of the oxidation mask removed. This avoids critical alignment in that the masking effect of the first part of the field oxide is used. After the doping treatment, a second oxidation treatment, is carried out to complete the field oxide.
    Type: Grant
    Filed: December 22, 1980
    Date of Patent: February 22, 1983
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4343079
    Abstract: A method of manufacturing an IGFET device in an entirely self-registering manner, in which on the semi-conductor body a narrow silicon nitride strip is formed which covers only the active region of the body and the width of which is substantially equal to that of the transistors to be manufactured and possibly other circuit elements. This nitride strip is used as a mask for providing the channel stopper zone and as an oxidation mask for providing a first oxide layer. The nitride strip is then etched in which the strip is locally removed over its entire width and only parts remain above the channel region and contact regions which form a second oxidation mask and, in cooperation with the first oxide layer, a doping mask. The source and drain zones of the transistors and possibly further zones, for example underpasses, are formed via said doping mask after which by oxidation a sunken oxide pattern is formed over the whole surface with the exception of the channel regions and the contact regions.
    Type: Grant
    Filed: April 18, 1980
    Date of Patent: August 10, 1982
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems
  • Patent number: 4127864
    Abstract: A semiconductor device having a bipolar transistor of the lateral type, preferably a pnp-transistor which is provided in a homogeneously doped semiconductor layer and which may be provided both in an n-type and in a p-type semiconductor layer and of which the base comprises a highly doped contact region and an associated substantially non-depleted active base region, while the emitter zone is situated substantially entirely within the active base region. Herewith, high frequency complementary transistors can be formed in a single epitaxial layer. The invention furthermore comprises a suitable method of manufacturing said transistor in which use is made of underetching.
    Type: Grant
    Filed: December 13, 1977
    Date of Patent: November 28, 1978
    Assignee: U.S. Philips Corporation
    Inventor: Pieter J. W. Jochems