Patents by Inventor Pieter Joost Adriaan Harpe

Pieter Joost Adriaan Harpe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230068336
    Abstract: A sensing system and method uses a sense electrode arrangement for coupling to a surface of a body such that the sense electrode arrangement and the body (and the spacing between them) define a coupling capacitance. First and second sensing circuits have different transfer functions and generate first and second outputs. These outputs are processed to determine the coupling capacitance. The electrophysiological signal being monitored is also acquired by one or both of the sensing circuits. In this way, the quality of the electrode coupling can be determined in a simple and passive manner.
    Type: Application
    Filed: January 21, 2021
    Publication date: March 2, 2023
    Inventors: MOHAMMED MEFTAH, SOTIR FILIPOV OUZOUNOV, YIJING ZHANG, PIETER JOOST ADRIAAN HARPE
  • Patent number: 8896476
    Abstract: A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time ?MV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time ?MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: November 25, 2014
    Assignee: Technische Universiteit Eindhoven
    Inventor: Pieter Joost Adriaan Harpe
  • Publication number: 20140210653
    Abstract: A successive operation register (SAR) analog-to-digital converter (ADC) circuit includes a bit reliability circuit that detects a delay time of the voltage comparator and, if the detected delay time is greater than a delay threshold time ?MV, outputs a bit reliability decision signal; a digital noise reduction circuit that is selectively activated if the bit reliability decision signal indicates the detected delay time is greater than the delay threshold time ?MV and produces a noise-reduced decision output that supersedes the decision output of the voltage comparator. In a preferred embodiment, the digital noise reduction circuit uses a multiple voting logic to produce a majority vote value as the noise-reduced decision output.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 31, 2014
    Inventor: Pieter Joost Adriaan Harpe