Patents by Inventor Pieter Schuddinck

Pieter Schuddinck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240429274
    Abstract: Provided herein is a nanosheet device that includes a first and a second transistor structure, each comprising a respective source region, drain region, and channel region extending between the respective source and drain regions, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure includes a first set of vertically stacked channel layers, wherein each channel layer of the first set of vertically stacked channel layers has an inward facing surface contacting a first side surface of the dielectric wall, and wherein the channel region of the second transistor structure includes a second set of vertically stacked channel layers, and wherein each channel layer of the second set of vertically stacked channel layers has an inward facing surface contacting a second side surface, opposite to the first side surface, of the dielectric wall
    Type: Application
    Filed: June 25, 2024
    Publication date: December 26, 2024
    Inventors: Geert Hellings, Pieter Schuddinck
  • Publication number: 20240204080
    Abstract: A method for forming a semiconductor device is provided. The method includes: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench; forming a second contact trench; and forming a first top S/D contact.
    Type: Application
    Filed: December 13, 2023
    Publication date: June 20, 2024
    Inventors: Boon Teik Chan, Hsiao-Hsuan Liu, Pieter Schuddinck
  • Publication number: 20230178554
    Abstract: Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Bilal Chehab, Pieter Schuddinck, Julien Ryckaert, Pieter Weckx
  • Patent number: 9601379
    Abstract: In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped nanowires at a location that corresponds to the channel region of the device, performing a selective etching process through a cavity to remove a second plurality of nanowires from the channel region and the source/drain regions of the device while leaving a first plurality of nanowires in position, and forming a metal conductive source/drain contact structure in each of the source/drain regions, wherein each of the metal conductive source/drain contact structures is positioned all around the first plurality of nanowires positioned in the source/drain regions.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: March 21, 2017
    Assignees: GLOBALFOUNDRIES Inc., IMEC VZW
    Inventors: Bartlomiej Jan Pawlak, Dmitry Yakimets, Pieter Schuddinck