Patents by Inventor Pieter Simon Van Dijk

Pieter Simon Van Dijk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrating silicon-BJT to a silicon-germanium-HBT manufacturing process
    Patent number: 10784257
    Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 22, 2020
    Assignee: NXP B.V.
    Inventors: Petrus Hubertus Cornelis Magnee, Pieter Simon van Dijk, Johannes Josephus Theodorus Marinus Donkers, Dolphin Abessolo Bidzo
  • INTEGRATING SILICON-BJT TO A SILICON-GERMANIUM-HBT MANUFACTURING PROCESS
    Publication number: 20200075585
    Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 5, 2020
    Inventors: Petrus Hubertus Cornelis Magnee, Pieter Simon van Dijk, Johannes Josephus Theodorus Marinus Donkers, Dolphin Abessolo Bidzo
  • Manufacturing a MEMS element having cantilever and cavity on a substrate
    Patent number: 8097483
    Abstract: Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode (5) and a second electrode (12; 25), the first and second electrodes being separated by a cavity (16; 32), the substrate including an insulating surface layer (3), the first electrode (5) being arranged on the insulating surface layer a first metal body (7a; 20) being adjacent to the first electrode and arranged as anchor of the second electrode (12; 25) the second electrode being arranged as a beam-shaped body (12; 25) located on the first metal body and above the first electrode; the cavity (16; 32) being laterally demarcated by a sidewall of the first metal body.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: January 17, 2012
    Assignee: Epcos AG
    Inventors: Robertus T. F. Van Schaijk, Piebe Anne Zijlstra, Ronald Koster, Pieter Simon Van Dijk
  • MANUFACTURING A MEMS ELEMENT HAVING CANTILEVER AND CAVITY ON A SUBSTRATE
    Publication number: 20100264498
    Abstract: Method for manufacturing a capacitor on a substrate, the capacitor including a first electrode (5) and a second electrode (12; 25), the first and second electrodes being separated by a cavity (16; 32), the substrate including an insulating surface layer (3), the first electrode (5) being arranged on the insulating surface layer a first metal body (7a; 20) being adjacent to the first electrode and arranged as anchor of the second electrode (12; 25) the second electrode being arranged as a beam-shaped body (12; 25) located on the first metal body and above the first electrode; the cavity (16; 32) being laterally demarcated by a sidewall of the first metal body.
    Type: Application
    Filed: October 15, 2008
    Publication date: October 21, 2010
    Applicant: EPCOS AG
    Inventors: Robertus T. F. Van Schaijk, Piebe Anne Zijlstra, Ronald Koster, Pieter Simon Van Dijk