Abstract: Solid-state circuit breakers and method of operating same are provided. A solid-state circuit breaker (SSCB) is configured to generate a first output representative of a current through a current path of the SSCB. An analog fault detection circuit is coupled with first output and is configured to assert a second output in response to the current exceeding a trip current level. At least one analog-to-digital converter (ADC) is configured to generate samples of the first output, where the at least one ADC has a di/dt detection bandwidth that is less than a di/dt detection bandwidth of the analog fault detection circuit. The SSCB is further configured to disable the current path through the SSCB in response to determining, asynchronously, that either the second output is being asserted by the analog fault detection circuit or the samples indicate that the current through the current path exceeds the trip current level.

Abstract: A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.

Abstract: Cooling arrangements are disclosed for solid state circuit breakers. In one arrangement, a MOV is disposed between two pulsating heat pipes. An IGCT is disposed on the other side of each pulsating heat pipe away from the MOV. In another arrangement, a bus bar is integral with a heat spreader disposed between a pulsating heat pipe and an IGCT.

Abstract: An overcurrent fault detector using a High Electron Mobility Transistor (HEMT) operated by a gate driver is disclosed. The overcurrent fault detector includes a band-pass filter and a control circuit. The band-pass filter is configured to receive gate-to-source voltage (VGS) signals of the HEMT and filter the VGS signals to generate a band-limited version of the VGS signals. The control circuit is configured to measure a value of the band-limited version of the VGS signals, determine if the value is greater than a threshold value, and generate a fault signal that disables the gate driver and terminates an overcurrent fault condition in response to determining that the value is greater than the threshold value.

Abstract: A bi-directional switch for an inductive machine is described. The bi-directional switch may include a first power semiconductor transistor with a first source, a first drain, and a first gate. The bi-directional switch may further include a second power semiconductor transistor with a second source, a second drain, and a second gate. The bi-directional switch may include the second source connected to the first source. The bi-directional switch may include a soft-starter device including a control circuit configurable to provide a first control signal to the first power semiconductor transistor and a second control signal to the second power semiconductor transistor.

Abstract: An electrical power cable is provided with two ends and an elongated length therebetween. The cable includes one or more conductors for conducting electrical power from a power source to an electrical load. One end includes a switch and a relay to provide electrical power to the electrical load and to disconnect an electrical contact from the power conductor.

Abstract: In one aspect, a solid-state circuit breaker (SSCB) is provided. The SSCB is configured to generate a first output representative of a current through a current path of the SSCB. An analog fault detection circuit is coupled with first output and is configured to assert a second output in response to the current exceeding a trip current level. At least one analog-to-digital converter (ADC) is configured to generate samples of the first output, where the at least one ADC has a di/dt detection bandwidth that is less than a di/dt detection bandwidth of the analog fault detection circuit. The SSCB is further configured to disable the current path through the SSCB in response to determining, asynchronously, that either the second output is being asserted by the analog fault detection circuit or the samples indicate that the current through the current path exceeds the trip current level.

Abstract: A gate driver circuit is provided that includes a turn-on path, a turn-off path, and a fast discharge path. The turn-on path is couplable between a gate of a solid-state switch and a voltage turn-on signal (VGON) from a gate driver, where the turn-on path defines a turn-on time for the solid-state switch. The turn-off path is couplable between the gate and a voltage turn-off signal (VGOFF) from the gate driver, where the turn-off path defines a turn-off time for the solid-state switch. The fast discharge path is selectively couplable in parallel with the turn-off path during a portion of a gate-to-source voltage (VGS) transition for the solid-state switch, where the turn-off path in parallel with the fast discharge path defines a turn-off delay for the solid-state switch and each of the turn-on time, the turn-off time, and the turn-off delay are independently configurable.

Abstract: A power semiconductor circuit is provided for clamping the voltage across the circuit when a power semiconductor switch is opened (i.e., turned off). The circuit may include a first surge arrester and a first semiconductor switch coupled in parallel with the power semiconductor switch. The first semiconductor switch is coupled in series with the first surge arrester. A second surge arrester may be coupled to the gate of the first semiconductor switch to control current flow through the first semiconductor switch and the first surge arrester.

Abstract: An electrification arrangement is provided for simplifying changes to the system, such as adding new electrical loads. The arrangement includes a power supply bus that routes available electric power throughout a facility. Electrical loads may be connected to the power supply bus using smart connectors that provide electrical protection and control of respective electrical loads.

Abstract: An overcurrent fault detector using a High Electron Mobility Transistor (HEMT) operated by a gate driver is disclosed. The overcurrent fault detector includes a band-pass filter and a control circuit. The band-pass filter is configured to receive gate-to-source voltage (VGS) signals of the HEMT and filter the VGS signals to generate a band-limited version of the VGS signals. The control circuit is configured to measure a value of the band-limited version of the VGS signals, determine if the value is greater than a threshold value, and generate a fault signal that disables the gate driver and terminates an overcurrent fault condition in response to determining that the value is greater than the threshold value.

Abstract: A bi-directional switch for an inductive machine is described. The bi-directional switch may include a first power semiconductor transistor with a first source, a first drain, and a first gate. The bi-directional switch may further include a second power semiconductor transistor with a second source, a second drain, and a second gate. The bi-directional switch may include the second source connected to the first source. The bi-directional switch may include a soft-starter device including a control circuit configurable to provide a first control signal to the first power semiconductor transistor and a second control signal to the second power semiconductor transistor.

Abstract: Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising a first semiconductor device and a second semiconductor device coupled together in a first anti-series configuration between a first terminal and a second terminal; a third semiconductor device and a fourth semiconductor device coupled together in a second anti-series configuration between the first terminal and the second terminal; a controller configured to operate the power switch to simultaneously conduct a first portion of a load current from the first terminal to the second terminal by closing the first semiconductor device and the second semiconductor device, and to conduct a second portion of the load current from the first terminal to the second terminal by closing the third semiconductor device and the fourth semiconductor device.

Abstract: A system and method for maintaining a temperature of a power system using a cooling system that includes an impeller and a phase change material. During normal operation of the cooling system, heat that is generated by the operation of an electronic device(s) of the power system can be transferred primarily by conduction through an upper base plate and fins of a heat sink, and dissipated via forced convection that is generated by the impeller. Additionally, the phase change material is positioned outside of a main heat flux path of the heat sink such that, during normal operation of the cooling system, the phase change material does not provide a heat flux obstruction. In the event of an impeller failure, the phase change material provides at least a temporary cooling source for an extended period of time via the relatively large latent heat capacity of the phase change material.

Abstract: A power semiconductor circuit is provided for clamping the voltage across the circuit when a power semiconductor switch is opened (i.e., turned off). The circuit may include a first surge arrester and a first semiconductor switch coupled in parallel with the power semiconductor switch. The first semiconductor switch is coupled in series with the first surge arrester. A second surge arrester may be coupled to the gate of the first semiconductor switch to control current flow through the first semiconductor switch and the first surge arrester.

Abstract: Systems, methods, techniques and apparatuses of power switches are disclosed. One exemplary embodiment is a power switch comprising a first semiconductor device and a second semiconductor device coupled together in a first anti-series configuration between a first terminal and a second terminal; a third semiconductor device and a fourth semiconductor device coupled together in a second anti-series configuration between the first terminal and the second terminal; a controller configured to operate the power switch to simultaneously conduct a first portion of a load current from the first terminal to the second terminal by closing the first semiconductor device and the second semiconductor device, and to conduct a second portion of the load current from the first terminal to the second terminal by closing the third semiconductor device and the fourth semiconductor device.

Abstract: Systems, methods, techniques and apparatuses of power switches are disclosed. One embodiment is a power switch comprising a first reverse blocking integrated gate-commutated thyristor (RB-IGCT); a second RB-IGCT coupled in an antiparallel configuration with the first RB-IGCT; a transient voltage suppressor coupled in parallel with the first RB-IGCT and the second RB-IGCT; and a controller. The controller is structured to determine a direction of a current flowing through the power switch, determine a magnitude of the current flowing through the power switch exceeds a threshold, and turn off the one of the first RB-IGCT and the second RB-IGCT receiving a current flowing in a reverse direction in response to determining the magnitude of the current flowing through the power switch exceeds the threshold.

Abstract: An electrification arrangement is provided for simplifying changes to the system, such as adding new electrical loads. The arrangement includes a power supply bus that routes available electric power throughout a facility. Electrical loads may be connected to the power supply bus using smart connectors that provide electrical protection and control of respective electrical loads.

Abstract: An electrical power cable is provided with two ends and an elongated length therebetween. The cable includes one or more conductors for conducting electrical power from a power source to an electrical load. One end includes a switch and a relay to provide electrical power to the electrical load and to disconnect an electrical contact from the power conductor.

Abstract: A system for providing bi-directional power flow and power conditioning for high-voltage applications. The system including a normally-off four-quadrant power electronic switch having two gates and two normally-on junction field-effect transistor. The normally-off four-quadrant power electronic switch and the two normally-on junction field-effect transistors are coupled to one another in a bi-cascode configuration.