Patents by Inventor Pietro Montanini

Pietro Montanini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11777034
    Abstract: A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 3, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Chen Zhang, Jingyun Zhang, Junli Wang, Pietro Montanini
  • Publication number: 20230197778
    Abstract: Embodiments herein include semiconductor structures with an active channel stack having an upper field-effect transistor (FET) and a lower FET vertically stacked below the upper FET The semiconductor structure may also include a dummy stub adjacent to the active channel stack, a lower source/drain (S/D) connected to the active channel stack and laterally extended over the dummy stub, and an upper S/D connected to the active channel stack above the lower S/D.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Ruilong Xie, Chen Zhang, Jingyun Zhang, PIETRO MONTANINI
  • Publication number: 20230178621
    Abstract: A nanosheet semiconductor device includes channel nanosheets each connected to a source/drain region that has a front surface, a rear surface, and an internal recess between the front surface and the rear surface. The device further includes a source/drain region contact in physical contact with the V shaped internal recess, with the front surface, and with the rear surface. The device may be fabricated by forming the source/drain region, recessing the source/drain region, and by forming a sacrificial source/drain region upon and around the recessed source/drain region. The sacrificial source/drain region may be removed and the source/drain region contact may be formed in place thereof.
    Type: Application
    Filed: December 7, 2021
    Publication date: June 8, 2023
    Inventors: Ruilong Xie, Reinaldo Vega, Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker, Pietro Montanini, Jingyun Zhang, Robert Robison
  • Publication number: 20230178617
    Abstract: Semiconductor channel layers vertically aligned and stacked one on top of another, separated by a gate stack material wrapping around the semiconductor channel layers, a heavily doped p-type field effect transistor (p-FET) source drain epitaxy region adjacent to the semiconductor channel layers, a horizontal lower surface of the p-FET source drain epitaxy region is adjacent to a horizontal upper surface of an undoped silicon epitaxy. Forming a first stack, second stack and third stack of nanosheet layers on a substrate, each including alternating layers of a sacrificial and a semiconductor channel vertically aligned and stacked one on top of another, forming a first sacrificial gate across the first stack, a second sacrificial gate across the second stack and a third sacrificial gate across the third stack, forming an undoped silicon epitaxy between the first and the second stacks and between the second and the third stacks.
    Type: Application
    Filed: December 3, 2021
    Publication date: June 8, 2023
    Inventors: Julien Frougier, Andrew M. Greene, Ruilong Xie, Lan Yu, PIETRO MONTANINI
  • Publication number: 20230099985
    Abstract: A semiconductor structure comprises a substrate defining a first axis and a second axis in orthogonal relation to the first axis, first and second nanosheet stacks disposed on the substrate, a gate structure on each of the first and second nanosheet stacks, a source/drain region adjacent each of the first and second nanosheet stacks, a wrap-around contact disposed about each source/drain region and an isolator pillar disposed between the wrap-around contacts.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Ruilong Xie, Oleg Gluschenkov, Andrew M. Greene, Pietro Montanini
  • Publication number: 20230075966
    Abstract: A stacked transistor device is provided. The stacked transistor device includes a nanosheet transistor device on a substrate; and a fin field effect transistor device over the nanosheet transistor device to form the stacked transistor device, wherein the fin field effect transistor device is configured to have a current flow through the fin field effect transistor device perpendicular to a current flow through the nanosheet transistor device.
    Type: Application
    Filed: September 7, 2021
    Publication date: March 9, 2023
    Inventors: Ruilong Xie, Chen Zhang, Jingyun Zhang, Junli Wang, Pietro Montanini
  • Patent number: 11575022
    Abstract: A semiconductor device structure and a method for fabricating the semiconductor device structure are disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Wenyu Xu, Ruilong Xie, Pietro Montanini, Hemanth Jagannathan
  • Publication number: 20220367626
    Abstract: A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.
    Type: Application
    Filed: July 11, 2022
    Publication date: November 17, 2022
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Andrew M. Greene, Pietro Montanini
  • Patent number: 11387319
    Abstract: A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: July 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Andrew M. Greene, Pietro Montanini
  • Patent number: 11201089
    Abstract: Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hiroaki Niimi, Pietro Montanini, Kangguo Cheng
  • Patent number: 11183583
    Abstract: VTFET devices with bottom source and drain extensions are provided. In one aspect, a method of forming a VTFET device includes: patterning vertical fin channels in a substrate; forming sidewall spacers along the vertical fin channels having a liner and a spacer layer; forming recesses at a base of the vertical fin channels; indenting the liner; annealing the substrate under conditions sufficient to reshape the recesses; forming bottom source and drains in the recesses; forming bottom source and drain extensions in the substrate adjacent to the bottom source and drains; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers alongside the vertical fin channels; forming top spacers over the gate stacks; and forming top source and drains at tops of the vertical fin channels. A VTFET device by the method having bottom source and drain extensions is also provided.
    Type: Grant
    Filed: April 25, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, Pietro Montanini
  • Publication number: 20210336035
    Abstract: VTFET devices with bottom source and drain extensions are provided. In one aspect, a method of forming a VTFET device includes: patterning vertical fin channels in a substrate; forming sidewall spacers along the vertical fin channels having a liner and a spacer layer; forming recesses at a base of the vertical fin channels; indenting the liner; annealing the substrate under conditions sufficient to reshape the recesses; forming bottom source and drains in the recesses; forming bottom source and drain extensions in the substrate adjacent to the bottom source and drains; removing the sidewall spacers; forming bottom spacers on the bottom source and drains; forming gate stacks over the bottom spacers alongside the vertical fin channels; forming top spacers over the gate stacks; and forming top source and drains at tops of the vertical fin channels. A VTFET device by the method having bottom source and drain extensions is also provided.
    Type: Application
    Filed: April 25, 2020
    Publication date: October 28, 2021
    Inventors: Shogo Mochizuki, Pietro Montanini
  • Publication number: 20210151583
    Abstract: A semiconductor device structure and a method for fabricating the semiconductor device structure are disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Wenyu XU, Ruilong Xie, Pietro MONTANINI, Hemanth JAGANNATHAN
  • Publication number: 20210074809
    Abstract: A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.
    Type: Application
    Filed: September 11, 2019
    Publication date: March 11, 2021
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Andrew M. Greene, Pietro Montanini
  • Patent number: 10937890
    Abstract: A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Wenyu Xu, Ruilong Xie, Pietro Montanini, Hemanth Jagannathan
  • Patent number: 10916627
    Abstract: A semiconductor device includes a plurality of nano sheet stacks disposed above a substrate. Each nanosheet stack has a first nanosheet and a first sacrificial layer, the first nanosheet and the first sacrificial layer each include a first end and a second end. The first end and the second end of the first sacrificial layer are recessed from the first and second ends of the first nanosheet. Each nanosheet stack has a bottom sacrificial layer formed on top of the substrate. The bottom sacrificial layer has a first end and a second end, which are recessed from the first and second ends of the first nanosheet. The semiconductor also has a source or drain (S/D) structures formed in contact with the first end and the second end of the first nanosheet. The S/D structures are isolated from the substrate by the bottom sacrificial layer.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Pietro Montanini
  • Publication number: 20200321448
    Abstract: A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 8, 2020
    Inventors: Wenyu XU, Ruilong Xie, Pietro MONTANINI, Hemanth JAGANNATHAN
  • Patent number: 10790393
    Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: September 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Eric R. Miller, Pietro Montanini
  • Publication number: 20200303500
    Abstract: A semiconductor device includes a plurality of nano sheet stacks disposed above a substrate. Each nanosheet stack has a first nanosheet and a first sacrificial layer, the first nanosheet and the first sacrificial layer each include a first end and a second end. The first end and the second end of the first sacrificial layer are recessed from the first and second ends of the first nanosheet. Each nanosheet stack has a bottom sacrificial layer formed on top of the substrate. The bottom sacrificial layer has a first end and a second end, which are recessed from the first and second ends of the first nanosheet. The semiconductor also has a source or drain (S/D) structures formed in contact with the first end and the second end of the first nanosheet. The S/D structures are isolated from the substrate by the bottom sacrificial layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Inventors: NICOLAS LOUBET, PIETRO MONTANINI
  • Publication number: 20200279780
    Abstract: Embodiments of the present invention are directed to techniques for forming a robust low-k bottom spacer for a vertical field effect transistor (VFET) using a spacer first, shallow trench isolation last process integration. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A first dielectric liner is formed on a sidewall of the semiconductor fin. A bottom spacer is formed over the substrate and on a sidewall of the first dielectric liner. The first dielectric liner is positioned between the semiconductor fin and the bottom spacer. Portions of the bottom spacer are removed to define a shallow trench isolation region.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Inventors: HIROKI NIIMI, PIETRO MONTANINI, KANGGUO CHENG