Abstract: A roughened silicon surface is formed by a process including repetitively performed roughening cycles. Each roughening cycles including a step for depositing a non-planar polymeric layer over an area of a silicon body and a step for plasma etching the polymeric layer and the area of the silicon body etch in a non-unidirectional way. As a result, a surface portion of the silicon body is removed, in a non-uniform way, to a depth not greater than 10 nm.

Abstract: A transducer includes a first substrate and an integrated circuit coupled to the first substrate. A sensor is electrically coupled to the integrated circuit and includes a second substrate having a first surface and a second surface opposite the first surface. The second substrate has scribe boundaries defining an outer edge of the second substrate and a chamber extending from the first surface towards but not reaching the second surface. A chamber extends from the second surface to meet the chamber from first surface. Scribe trenches in the second surface at the scribe boundaries have a width from the scribe boundary towards the chamber extending from the second surface. A membrane extends over the first surface and over the chamber extending from first surface. A plate extends from the first surface of the second substrate over the membrane.

Abstract: A roughened silicon surface is formed by a process including repetitively performed roughening cycles. Each roughening cycles including a step for depositing a non-planar polymeric layer over an area of a silicon body and a step for plasma etching the polymeric layer and the area of the silicon body etch in a non-unidirectional way. As a result, a surface portion of the silicon body is removed, in a non-uniform way, to a depth not greater than 10 nm.

Abstract: A transducer includes a first substrate and an integrated circuit coupled to the first substrate. A sensor is electrically coupled to the integrated circuit and includes a second substrate having a first surface and a second surface opposite the first surface. The second substrate has scribe boundaries defining an outer edge of the second substrate and a chamber extending from the first surface towards but not reaching the second surface. A chamber extends from the second surface to meet the chamber from first surface. Scribe trenches in the second surface at the scribe boundaries have a width from the scribe boundary towards the chamber extending from the second surface. A membrane extends over the first surface and over the chamber extending from first surface. A plate extends from the first surface of the second substrate over the membrane.

Abstract: A method of forming semiconductor devices, such as capacitive type MEMS acoustic transducers, in a semiconductor includes forming a mask layer on a back surface of the semiconductor wafer and removing first etch portions of the mask layer and scribe trench portions of the mask layer. Each scribe trench portion is positioned in the mask layer to define a corresponding scribe boundary of a plurality of the semiconductor devices being formed in the semiconductor wafer. Etching the semiconductor wafer through the first etch portions and the scribe trench portions may be done simultaneously to form external back chambers and scribe trenches, respectively, in the semiconductor wafer. The semiconductor wafer is then cut along cutting lines in the scribe trenches to singulate individual MEMS acoustic transducers. The etching through the first and second etch portions and the scribe trench portions are dry etching of the semiconductor substrate in one embodiment.

Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.

Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.

Abstract: Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.

Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.

Abstract: Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

Abstract: Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

Abstract: Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.

Abstract: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.

Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region a heater structure is first formed and a phase change layer is deposited on and in contact with the heater structure. Then, the phase change layer and the heater structure are defined by subsequent self-aligned etch steps.

Abstract: A phase change memory includes a cup-shaped heater element formed above a body. A tapered phase change region is formed on the cup-shaped heater element. The cup-shaped heater element is formed by depositing a stop layer of a first dielectric material over the body. A first sacrificial layer is deposited over the stop layer, the first sacrificial layer being of a second dielectric material that can be etched selectively with respect to the first dielectric material. An opening is etched in the first sacrificial layer and the stop layer. A heating layer is formed in the opening. The opening is filled with a filling material to obtain a structure having a cup-shaped heating region formed in the stop layer and excess portions extending over said stop layer. The excess portions by an etch selective with respect to the first dielectric material are removed.

Abstract: A phase change memory cell includes a phase change layer of a phase change material on a semiconductor body. A hard mask structure is formed on the phase change layer and a resist mask is formed on the hard mask structure. A hard mask is formed by shaping the hard mask structure using the resist mask. The phase change layer is shaped using the hard mask. The resist mask is removed before shaping the phase change layer.

Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element in a semiconductor wafer and a storage region of a phase change material on and in contact with the heater element. In order to form the heater element and the phase change storage region a heater structure is first formed and a phase change layer is deposited on and in contact with the heater structure. Then, the phase change layer and the heater structure are defined by subsequent self-aligned etch steps.