Patents by Inventor Pietro Piersimoni
Pietro Piersimoni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7145799Abstract: An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.Type: GrantFiled: June 30, 2005Date of Patent: December 5, 2006Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Pietro Piersimoni, Tommaso Vali
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Patent number: 7136307Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.Type: GrantFiled: May 6, 2005Date of Patent: November 14, 2006Assignee: Micron Technology, Inc.Inventors: Pietro Piersimoni, Pasquale Pistilli
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Patent number: 7028135Abstract: A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.Type: GrantFiled: August 28, 2002Date of Patent: April 11, 2006Assignee: Micron Technology, Inc.Inventors: Pietro Piersimoni, Pasquale Pistilli, Elio D'Ambrosio
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Patent number: 7027331Abstract: A system and method for a write state machine for a non-volatile memory. The write state machine has an associated read only memory (ROM) for storing instructions for operation of the non-volatile memory. The ROM is coupled to an input of a write state machine. An instruction needed to perform an algorithm is stored as a micro-instruction in the ROM such that an instruction sequence is changed by only reprogramming the ROM.Type: GrantFiled: August 4, 2004Date of Patent: April 11, 2006Assignee: Micron Technology, Inc.Inventors: Pietro Piersimoni, Pasquale Pistilli
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Publication number: 20050237804Abstract: An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.Type: ApplicationFiled: June 30, 2005Publication date: October 27, 2005Inventors: Giovanni Naso, Pietro Piersimoni, Tommaso Vali
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Patent number: 6947323Abstract: An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.Type: GrantFiled: October 31, 2003Date of Patent: September 20, 2005Assignee: Micron Technology, Inc.Inventors: Giovanni Naso, Pietro Piersimoni, Tommaso Vali
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Publication number: 20050195655Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.Type: ApplicationFiled: May 6, 2005Publication date: September 8, 2005Inventors: Pietro Piersimoni, Pasquale Pistilli
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Patent number: 6879522Abstract: A method for making a memory device includes forming or fabricating on a first substrate a first array of memory cells, a first read only memory, and a first write state machine which receives instructions from the first read only memory for operating the first array of memory cells. The method further includes forming or fabricating on a second substrate, a second array of memory cells, a second read only memory, and a second write state machine which receives instructions from the second read only memory for operating the second array of memory cells.Type: GrantFiled: June 10, 2003Date of Patent: April 12, 2005Assignee: Micron Technology, Inc.Inventors: Pietro Piersimoni, Pasquale Pistilli
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Publication number: 20050005060Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.Type: ApplicationFiled: August 4, 2004Publication date: January 6, 2005Inventors: Pietro Piersimoni, Pasquale Pistilli
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Publication number: 20040151026Abstract: An improved Flash memory device is described with a protection register lock bit erase enable circuit. A bond pad coupled to the lock bit erase enable circuit of the improved Flash memory is not bonded when the individual Flash memory chip wafer is packaged. This allows the memory manufacturer to access the bond pad and erase the lock bits while the chip is still in wafer form via a test card probe, but makes the lock bits effectively uneraseable when the chip wafer is packaged. This enables the memory chip manufacturer to enhance reliability and fault tolerance of the Flash memory device by thoroughly testing the lock bits and protection register functionality. Additionally, the lock bit erase enable circuit increases manufacturing flexibility by allowing the memory chip manufacturer to reprogram the protection register and lock bits in case of organizational changes or inadvertent or erroneous programming of the protection register.Type: ApplicationFiled: October 31, 2003Publication date: August 5, 2004Applicant: Micron Technology, Inc.Inventors: Giovanni Naso, Pietro Piersimoni, Tommaso Vali
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Publication number: 20040047181Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.Type: ApplicationFiled: June 10, 2003Publication date: March 11, 2004Inventors: Pietro Piersimoni, Pasquale Pistilli
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Patent number: 6618291Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The system includes an array of memory cells and a write state machine for controlling operations on the array of memory cells. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory. The write state machine is adapted to suspend an execution of one of the operations during an action on a block in the non-volatile memory which is not being accessed by the write state machine.Type: GrantFiled: March 12, 2001Date of Patent: September 9, 2003Assignee: Micron Technology, Inc.Inventors: Pietro Piersimoni, Pasquale Pistilli
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Publication number: 20030062938Abstract: A multiple partition memory array has a command user interface for each partition, and a logic interface. The logic interface receives signals from each of the command user interfaces to restrict executable commands in the command user interfaces to those commands that will not tax the system given the current status of each of the command user interfaces.Type: ApplicationFiled: August 28, 2002Publication date: April 3, 2003Inventors: Pietro Piersimoni, Pasquale Pistilli, Elio D'Ambrosio
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Publication number: 20020114182Abstract: A system and method for a write state machine for non-volatile memory is disclosed. The write state machine has an associated read only memory for storing instructions for operation of the non-volatile memory.Type: ApplicationFiled: March 12, 2001Publication date: August 22, 2002Inventors: Pietro Piersimoni, Pasquale Pistilli
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Patent number: 5874849Abstract: A charge pump 1 for operation in an integrated circuit having a power source Vdd. The pump is made of a plurality of pump cells 10 connected together. Each pump cell includes an inverter 50 having a port 42 to receive a negative bias input, a port 44 to receive a positive bias input, a port 38 to receive a clock input, and a port 40 to output an output clock signal at the same frequency of the clock input, but phase shifted by a predetermined amount determined by the signal levels of the negative bias and said positive bias. Also included in each pump cell is a capacitor 26. A circuit 20, 22, 24, for coupling the output clock signal to one port of the capacitor is also provided, as is a pair of diodes 28, 30, connected serially together, one end of the pair being connected to the power source and the other end 48 of the pair providing the output signal of the pump cell, the common point of the pair being connected to the other port of the capacitor.Type: GrantFiled: July 19, 1996Date of Patent: February 23, 1999Assignee: Texas Instruments IncorporatedInventors: Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Michael C. Smayling
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Patent number: 5844839Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.Type: GrantFiled: July 19, 1996Date of Patent: December 1, 1998Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Cristina Lattaro
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Patent number: 5732021Abstract: A method for selectibly erasing one or more non-volatile programmable memory cells in an integrated circuit. The method is applicable to an array 1 of memory cells 10 fabricated in a semiconductor substrate 30 of a first conductivity type semiconductor material, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. The cells should be formed in a first well 33 of said first conductivity type semiconductor material, the first wells being formed in second wells 31 of a second conductivity type semiconductor material, the first wells including cells in groups of one or more. The method involves the steps of applying a high voltage source to a selected one or more column lines, applying a zero voltage source to a selected one or more row lines; and applying the high voltage source to non-selected row lines.Type: GrantFiled: July 19, 1996Date of Patent: March 24, 1998Inventors: Michael C. Smayling, Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Cristina Lattaro
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Patent number: 5717634Abstract: A non-volatile, integrated circuit memory, such as a Flash EPROM, including an array 1 of memory cells 10, each cell having a floating gate 14 for programming the cell and a control gate 11 for reading the cell, the array having a plurality of row lines 15, a plurality of column lines 25 and a plurality of output lines 18. Included is a decoder circuit 16 having a plurality of input lines 94, 96, for each row in the array, and having as outputs the row lines 15. The decoder circuit includes a decoder logic circuit associated with each row line, the decoder logic circuit including a plurality of low power logic devices 84-90 interconnected to perform a predetermined decoding function on the signals on the input lines for the associated row line to apply a signal to an associated row node when the decoder logic circuit determines that the associated row line is selected.Type: GrantFiled: July 19, 1996Date of Patent: February 10, 1998Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Giulio Marotta, Giovanni Santin, Pietro Piersimoni
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Patent number: 5715195Abstract: A method for automatically detecting and correcting the underprogramming of a memory cell 10 in a non-volatile, progrommable memory array 1, the array having a plurality of such cells, each such cell being programmable by a progromming step that stores charge therein and being erasable by an erasing step that removes charge therefrom, and each such cell being readable to determine whether such cell is in a progrommed state or in an erased state. First, charge is stored in a selected cell therein 74. Then the selected cell is read to determine whether the selected cell is programmed 78. If the step of reading does not determine such cell to be programmed 80, the steps of storing and reading are automatically repeated until either the step of sensing indicates a sufficiently programmed cell or, alternatively, until a predermined number of iterations of the steps has been performed 86.Type: GrantFiled: July 19, 1996Date of Patent: February 3, 1998Assignee: Texas Instruments IncorporatedInventors: Michael C. Smayling, Giulio Marotta, Giovanni Santin, Pietro Piersimoni, Cristina Lattaro