Patents by Inventor Pijush Bhattacharya

Pijush Bhattacharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230183569
    Abstract: Halide-based scintillator materials, and related systems and methods are generally described. In some embodiments, the scintillator materials are thallium-based and/or have a perovskite structure. Specific embodiments of thallium calcium halides and thallium magnesium halides with desirable scintillation properties are provided.
    Type: Application
    Filed: August 3, 2022
    Publication date: June 15, 2023
    Applicant: Radiation Monitoring Devices, Inc.
    Inventors: Edgar V. Van Loef, Jaroslaw Glodo, Pijush Bhattacharya, Lakshmi Soundara Pandian, Kanai S. Shah
  • Patent number: 9638809
    Abstract: A combined thermal neutron detector and gamma-ray spectrometer system, including: a first detection medium including a lithium chalcopyrite crystal operable for detecting neutrons; a gamma ray shielding material disposed adjacent to the first detection medium; a second detection medium including one of a doped metal halide, an elpasolite, and a high Z semiconductor scintillator crystal operable for detecting gamma rays; a neutron shielding material disposed adjacent to the second detection medium; and a photodetector coupled to the second detection medium also operable for detecting the gamma rays; wherein the first detection medium and the second detection medium do not overlap in an orthogonal plane to a radiation flux. Optionally, the first detection medium includes a 6LiInSe2 crystal. Optionally, the second detection medium includes a SrI2(Eu) scintillation crystal.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 2, 2017
    Assignees: Consolidated Nuclear Security, LLC, Fisk University
    Inventors: Ashley C. Stowe, Arnold Burger, Pijush Bhattacharya, Yevgeniy Tupitsyn
  • Publication number: 20170090045
    Abstract: A combined thermal neutron detector and gamma-ray spectrometer system, including: a first detection medium including a lithium chalcopyrite crystal operable for detecting neutrons; a gamma ray shielding material disposed adjacent to the first detection medium; a second detection medium including one of a doped metal halide, an elpasolite, and a high Z semiconductor scintillator crystal operable for detecting gamma rays; a neutron shielding material disposed adjacent to the second detection medium; and a photodetector coupled to the second detection medium also operable for detecting the gamma rays; wherein the first detection medium and the second detection medium do not overlap in an orthogonal plane to a radiation flux. Optionally, the first detection medium includes a 6LiInSe2 crystal. Optionally, the second detection medium includes a SrI2(Eu) scintillation crystal.
    Type: Application
    Filed: August 7, 2014
    Publication date: March 30, 2017
    Applicants: Consolidated Nuclear Security, LLC, Fisk University
    Inventors: Ashley C. STOWE, Arnold BURGER, Pijush BHATTACHARYA, Yevgeniy TUPITSYN
  • Publication number: 20160041273
    Abstract: A combined thermal neutron detector and gamma-ray spectrometer system, including: a first detection medium including a lithium chalcopyrite crystal operable for detecting neutrons; a gamma ray shielding material disposed adjacent to the first detection medium; a second detection medium including one of a doped metal halide, an elpasolite, and a high Z semiconductor scintillator crystal operable for detecting gamma rays; a neutron shielding material disposed adjacent to the second detection medium; and a photodetector coupled to the second detection medium also operable for detecting the gamma rays; wherein the first detection medium and the second detection medium do not overlap in an orthogonal plane to a radiation flux. Optionally, the first detection medium includes a 6LiInSe2 crystal. Optionally, the second detection medium includes a SrI2(Eu) scintillation crystal.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 11, 2016
    Applicants: Consolidated Nuclear Security, LLC, Fisk University
    Inventors: Ashley C. STOWE, Arnold BURGER, Pijush BHATTACHARYA, Yevgeniy TUPITSYN
  • Patent number: 7081371
    Abstract: A stable, wide-bandgap (approximately 6 eV) ZnO/MgO multilayer thin film is fabricated using pulsed-laser deposition on c-plane Al2O3 substrates. Layers of ZnO alternate with layers of MgO. The thickness of MgO is a constant of approximately 1 nm; the thicknesses of ZnO layers vary from approximately 0.75 to 2.5 nm. Abrupt structural transitions from hexagonal to cubic phase follow a decrease in the thickness of ZnO sublayers within this range. The band gap of the thin films is also influenced by the crystalline structure of multilayer stacks. Thin films with hexagonal and cubic structure have band-gap values of 3.5 and 6 eV, respectively. In the hexagonal phase, Mg content of the films is approximately 40%; in the cubic phase Mg content is approximately 60%. The thin films are stable and their structural and optical properties are unaffected by annealing at 750° C.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: July 25, 2006
    Assignee: University of Puerto Rico
    Inventors: Ram S. Katiyar, Pijush Bhattacharya, Rasmi R. Das
  • Patent number: 5811851
    Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: September 22, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5656852
    Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 12, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5605858
    Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g. TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: February 25, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5554866
    Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: September 10, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5554564
    Abstract: An improved method of forming a capacitor electrode for a microelectronic structure such as a dynamic read only memory is disclosed which has a high dielectric constant (HDC) material as a capacitor dielectric. According to an embodiment of the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: September 10, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-ho Park, Pijush Bhattacharya
  • Patent number: 5489548
    Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: February 6, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Scott R. Summerfelt, Kyung-Ho Park, Pijush Bhattacharya