Patents by Inventor Pik Shen Chee

Pik Shen Chee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ENABLING UNIVERSAL CORE MOTHERBOARD WITH FLEXIBLE INPUT-OUTPUT PORTS
    Publication number: 20240104043
    Abstract: Embodiments herein relate to a module which can be inserted into or removed from a computing device by a user. The module includes an input-output port which is configured for a desired specification, such as USB-A, USB-C, Thunderbolt, DisplayPort or HDMI. The port can be provided on an expansion card such as an M.2 card for communicating with a host platform. The host platform can communicate with different types of modules in a standardized way so that complexity and costs are reduced. In another aspect, with a dual port module, the host platform can concurrently send/receive power through one port and send/receive data from the other port.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Shailendra Singh Chauhan, Nirmala Bailur, Reza M. Zamani, Jackson Chung Peng Kong, Charuhasini Sunder Raman, Venkataramani Gopalakrishnan, Chuen Ming Tan, Sreejith Satheesakurup, Karthi Kaliswamy, Venkata Mahesh Gunnam, Yi Jen Huang, Kie Woon Lim, Dhinesh Sasidaran, Pik Shen Chee, Venkataramana Kotakonda, Kunal A. Shah, Ramesh Vankunavath, Siva Prasad Jangili Ganga, Ravali Pampala, Uma Medepalli, Tomer Savariego, Naznin Banu Wahab, Sindhusha Kodali, Manjunatha Venkatarauyappa, Surendar Jeevarathinam, Madhura Shetty, Deepak Sharma, Rohit Sharad Mahajan
  • Performing an atomic operation without quiescing an interconnect structure
    Patent number: 9015436
    Abstract: In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of this message, logic of the processor can write an entry in a tracking buffer of the processor for the address and thereafter allow a transaction to be sent from the processor via an interconnect if an address of the transaction does not match any address stored in the tracking buffer. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventor: Pik Shen Chee
  • Performing An Atomic Operation Without Quiescing An Interconnect Structure
    Publication number: 20130054915
    Abstract: In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of this message, logic of the processor can write an entry in a tracking buffer of the processor for the address and thereafter allow a transaction to be sent from the processor via an interconnect if an address of the transaction does not match any address stored in the tracking buffer. Other embodiments are described and claimed.
    Type: Application
    Filed: August 22, 2011
    Publication date: February 28, 2013
    Inventor: Pik Shen Chee