Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. Garbage collection is performed with regard to the memory device on the basis of a first amount of time and a second amount of time, the first amount of time being a period of time between triggering of first garbage collection and triggering of second garbage collection, and the second amount of time being an amount of time necessary to perform the second garbage collection. A ratio of the first amount of time to the second amount of time is determined as a target ratio value, and the second amount of time is determined to be equal to or longer than a minimum garbage collection operation time. Accordingly, efficient garbage collection can be performed, and the optimal time to perform garbage collection can be determined with regard to a configured performance drop value.

Abstract: Proposed are an apparatus and a method for NCR-based beam search in a wireless communication system. A beam search procedure performed by a network-controlled repeater (NCR) in a wireless communication system includes performing carrier sensing under control of a base station to set a communication-possible area, limiting a beam candidate group on the basis of the communication-possible area to shorten the time taken for beam search, and continuing the carrier sensing even after the beam search procedure is initiated, to update the beam candidate group.

Abstract: A system for automatically washing and sterilizing a heat exchanger of a system air conditioner is proposed. The system for automatically washing and sterilizing a heat exchanger of a system air conditioner according to an embodiment includes: a washer body including an air compressor, a compressed air tank, a detergent liquid tank, a washing water tank, a washing water tank, a high-pressure pump, a hot air generator, a steam generator, and a hot air generator; a washing module that sprays washing water, etc., supplied from the ground during rotation thereof to a cooling fin by a spray nozzle, thus washing the cooling fin; a waste water collection vinyl cover that collects waste water dropping when the cooling fin is washed; and a controller configured to control the washing module that sprays washing water, etc., to the cooling fin.

Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.

Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.

Abstract: A method of a first user equipment (UE) may comprise: receiving a downlink (DL) reference signal transmitted by a base station using a beam included in a beam candidate group to be used for sidelink (SL) communication with a second UE; measuring a DL reference signal received power (RSRP) of the DL reference signal; determining a transmit power of a beam included in the beam candidate group based on the measured DL RSRP; and transmitting SL data to the second UE with the determined transmit power.

Abstract: An operation method of a relay node may include: receiving, from a first communication node, first data composed of n bits; receiving, from a second communication node, second data composed of m bits; in response to determining that n is greater than m, generating first T-data of m bits excluding (n-m) bits from the n-bits of the first data and first R-data of (n-m) bits; generating third data by performing a network coding operation on the first T-data and the second data; transmitting the third data to the first communication node; and transmitting the third data and the first R-data to the second communication node.

Abstract: Disclosed are a relay method and device in a communication system. An operation method of a first communication node comprises the steps of: transmitting a reference signal to one or more candidate R nodes; receiving first feedback information including a minimum value of a first RSRP from a first candidate R node belonging to the one or more candidate R nodes; receiving second feedback information including a minimum value of a second RSRP from a second candidate R node belonging to the one or more candidate R nodes; comparing a first value based on the first feedback information with a second value based on the second feedback information; when the first value is greater than the second value, selecting the first candidate R node as an R node that is to perform a relaying operation; and communicating with a second communication node via the R node.

Abstract: A method of a transmitting terminal may include: setting an initial beam pairing flag indicating that the transmitting terminal transmitting sidelink-synchronization signal blocks (S-SSBs) is not a synchronization reference terminal; transmitting a plurality of S-SSBs including the initial beam pairing flag in a beam sweeping scheme; receiving, from a receiving terminal, information on a preferred beam among a plurality of beams through which the plurality of S-SSBs are transmitted; and transmitting data to the receiving terminal using the preferred beam.

Abstract: An operation method of a first terminal may include: transmitting a plurality of sidelink-synchronization signal blocks (S-SSBs); performing a monitoring operation on a plurality of response resources associated with the plurality of S-SSBs; receiving a first response signal from a second terminal in a first response resource among the plurality of response resources; identifying a first S-SSB associated with the first response resource among the plurality of S-SSBs; and determining a first transmission beam through which the first S-SSB is transmitted among a plurality of transmission beams of the first terminal as an optimal transmission beam.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. Garbage collection is performed with regard to the memory device on the basis of a first amount of time and a second amount of time, the first amount of time being a period of time between triggering of first garbage collection and triggering of second garbage collection, and the second amount of time being an amount of time necessary to perform the second garbage collection. A ratio of the first amount of time to the second amount of time is determined as a target ratio value, and the second amount of time is determined to be equal to or longer than a minimum garbage collection operation time. Accordingly, efficient garbage collection can be performed, and the optimal time to perform garbage collection can be determined with regard to a configured performance drop value.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. Garbage collection is performed with regard to the memory device on the basis of a first amount of time and a second amount of time, the first amount of time being a period of time between triggering of first garbage collection and triggering of second garbage collection, and the second amount of time being an amount of time necessary to perform the second garbage collection. A ratio of the first amount of time to the second amount of time is determined as a target ratio value, and the second amount of time is determined to be equal to or longer than a minimum garbage collection operation time. Accordingly, efficient garbage collection can be performed, and the optimal time to perform garbage collection can be determined with regard to a configured performance drop value.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.

Abstract: An operation method of a relay node may include: receiving, from a first communication node, first data composed of n bits; receiving, from a second communication node, second data composed of m bits; in response to determining that n is greater than m, generating first T-data of m bits excluding (n?m) bits from the n-bits of the first data and first R-data of (n?m) bits; generating third data by performing a network coding operation on the first T-data and the second data; transmitting the third data to the first communication node; and transmitting the third data and the first R-data to the second communication node.

Abstract: An operation method of an IAB node in a communication system may comprise: measuring a power difference between a first signal received from a first node and a second signal received from a second node; controlling a transmit power of each of the first node and the second node based on the power difference; generating scheduling information for allowing the first node and the second node to simultaneously transmit signals; transmitting the scheduling information to the first node and the second node; and receiving signals that the first node and the second node simultaneously transmit according to the scheduling information by using the transmit power.

Abstract: A system for automatically washing and sterilizing a heat exchanger of a system air conditioner is proposed. The system for automatically washing and sterilizing a heat exchanger of a system air conditioner according to an embodiment includes: a washer body including an air compressor, a compressed air tank, a detergent liquid tank, a washing water tank, a washing water tank, a high-pressure pump, a hot air generator, a steam generator, and a hot air generator; a washing module that sprays washing water, etc., supplied from the ground during rotation thereof to a cooling fin by a spray nozzle, thus washing the cooling fin; a waste water collection vinyl cover that collects waste water dropping when the cooling fin is washed; and a controller configured to control the washing module that sprays washing water, etc., to the cooling fin.

Abstract: An operation method of a first terminal, performed in a communication system, may comprise receiving sidelink resource allocation information from a base station; receiving a first sidelink signal from a second terminal based on the sidelink resource allocation information; calculating a path loss experienced by the first sidelink signal based on the first sidelink signal; transmitting a second sidelink signal including information on the path loss experienced by the first sidelink signal to the second terminal; and receiving, from the second terminal, a third sidelink signal to which a sidelink transmit power determined based on the path loss is allocated.

Abstract: A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks, wherein the plurality of memory blocks includes one or more first memory blocks, each storing at least invalid data and one or more second memory blocks, each of which is blank. The controller is configured to determine a time or a period for performing garbage collection to secure an additional second memory block based at least on a transition speed representing a speed in which the second memory blocks is converted to the first memory blocks, the transition speed being determined based on a change between a first count of the first memory blocks and a second count of the second memory blocks.