Patents by Inventor Pil Je Sung
Pil Je Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240266189Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: ApplicationFiled: April 15, 2024Publication date: August 8, 2024Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 11961742Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: GrantFiled: August 23, 2021Date of Patent: April 16, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Publication number: 20220148886Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: ApplicationFiled: August 23, 2021Publication date: May 12, 2022Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 11101144Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: GrantFiled: December 23, 2019Date of Patent: August 24, 2021Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Publication number: 20200303212Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: ApplicationFiled: December 23, 2019Publication date: September 24, 2020Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 10515825Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: GrantFiled: September 18, 2018Date of Patent: December 24, 2019Assignee: Amkor Technology, Inc.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Publication number: 20190067035Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: ApplicationFiled: September 18, 2018Publication date: February 28, 2019Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 10079157Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: GrantFiled: December 22, 2015Date of Patent: September 18, 2018Assignee: Amkor Technology, Inc.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 9793180Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly.Type: GrantFiled: June 24, 2014Date of Patent: October 17, 2017Assignee: AMKOR TECHNOLOGY, INC.Inventors: Seo Yeon Ahn, Doo Hyun Park, Pil Je Sung, Won Chul Do, Young Rae Kim, Seung Chul Han, Joo Hyun Kim, Jong Sik Paek
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Patent number: 9449946Abstract: Disclosed are a semiconductor device and a manufacturing method thereof, which can achieve miniaturization and improvement in the integration level by forming a substrate using a pattern layer implemented on a wafer in a semiconductor fabrication (FAB) process. In one exemplified embodiment, the manufacturing method of the semiconductor device includes preparing a first semiconductor die including a plurality of through electrodes and a plurality of first conductive pillars, mounting the first semiconductor die to connect the first conductive pillars to the pattern layer provided on a wafer, forming a first encapsulant to cover the pattern layer and the first semiconductor die, mounting a second semiconductor die to electrically connect second conductive pillars provided in the second semiconductor die to the plurality of through electrodes exposed to a second surface of the first semiconductor die, and removing the wafer from a first surface of the pattern layer.Type: GrantFiled: March 18, 2014Date of Patent: September 20, 2016Assignee: Amkor Technology, Inc.Inventors: Pil Je Sung, Seong Min Seo, Jong Sik Paek, Seo Yeon Ahn, Hui Tae Kim
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Publication number: 20160189980Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.Type: ApplicationFiled: December 22, 2015Publication date: June 30, 2016Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Sung Geun Kang, Yong Song, Wang Gu Lee, Eun Young Lee, Seo Yeon Ahn, Pil Je Sung
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Patent number: 9190370Abstract: A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.Type: GrantFiled: May 29, 2015Date of Patent: November 17, 2015Assignee: Amkor Technology, Inc.Inventors: Jong Sik Paek, Doo Hyun Park, Won Chul Do, Pil Je Sung, Jin Hee Park, Do Hyung Kim, In Bae Park, Chang Min Lee, Yong Song, Sung Geun Kang
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Publication number: 20150262945Abstract: A method for a semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include bonding a first semiconductor die to a second semiconductor die, the first semiconductor die having a first surface comprising bond pads, a second surface opposite the first surface that is bonded to a first surface of the second semiconductor die, and sloped sides surfaces between the first and second surfaces of the first semiconductor die, such that a cross-section of the first semiconductor die is trapezoidal in shape. A passivation layer may be formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die. A redistribution layer may be formed on the passivation layer formed on the first surface and sloped side surfaces of the first semiconductor die and the first surface of the second semiconductor die.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Inventors: Jong Sik Paek, Doo Hyun Park, Won Chul Do, Pil Je Sung, Jin Hee Park, Do Hyung Kim, In Bae Park, Chang Min Lee, Yong Song, Sung Geun Kang
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Publication number: 20150255426Abstract: A semiconductor device with reduced warpage is disclosed and may, for example, include bonding at least two semiconductor die to a substrate, forming underfill material between the at least two semiconductor die and the substrate and between the at least two semiconductor die, and removing a portion of the underfill material between the at least two semiconductor die, thereby forming a groove. The at least two semiconductor die and the underfill material may, for example, be encapsulating utilizing an encapsulant. The groove may, for example, be filled using the encapsulant. The underfill material between the at least two semiconductor die may, for example, be removed utilizing laser etching. The underfill material between the at least two semiconductor die may, for example, be removed to a depth of 60-70% of a thickness of the at least two semiconductor die.Type: ApplicationFiled: November 18, 2014Publication date: September 10, 2015Inventors: Seung Nam Son, Pil Je Sung, Won Chul Do, JungBae Lee, Ji Hun Lee
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Publication number: 20150206807Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly.Type: ApplicationFiled: June 24, 2014Publication date: July 23, 2015Inventors: Seo Yeon Ahn, Doo Hyun Park, Pil Je Sung, Won Chul Do, Young Rae Kim, Seung Chul Han, Joo Hyun Kim, Jong Sik Paek
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Patent number: 9048241Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.Type: GrantFiled: October 25, 2013Date of Patent: June 2, 2015Assignee: Amkor Technology, Inc.Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Won Chul Do, Pil Je Sung, Jin Hee Park, Do Hyung Kim, In Bae Park, Chang Min Lee, Yong Song, SungGeun Kang
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Publication number: 20150041980Abstract: A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die.Type: ApplicationFiled: August 6, 2014Publication date: February 12, 2015Inventors: Seo Yeon Ahn, Pil Je Sung, Doo Hyun Park, Jong Sik Paek, Young Rae Kim, Hui Tae Kim, Yong Song, Seok Woo Yun
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Publication number: 20150014830Abstract: A semiconductor device utilizing redistribution layers to couple stacked die is disclosed and may include a first semiconductor die with a first surface comprising bond pads, a second surface opposite the first surface, and sloped side surfaces between the first and second surfaces, such that a cross-section of the first die is trapezoidal in shape. A second semiconductor die with a first surface may be bonded to the second surface of the first die, wherein the first surface of the second die may comprise bond pads. A passivation layer may be formed on the first surface and sloped side surfaces of the first die and the first surface of the second die. A redistribution layer may be formed on the passivation layer, electrically coupling bond pads on the first and second die. A conductive pillar may extend from a bond pad on the second die to the second redistribution layer.Type: ApplicationFiled: October 25, 2013Publication date: January 15, 2015Inventors: Jong Sik Paek, Doo Hyun Park, Seong Min Seo, Won Chul Do, Pil Je Sung, Jin Hee Park, Do Hyung Kim, In Bae Park, Chang Min Lee, Yong Song, SungGeun Kang
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Publication number: 20140284785Abstract: Disclosed are a semiconductor device and a manufacturing method thereof, which can achieve miniaturization and improvement in the integration level by forming a substrate using a pattern layer implemented on a wafer in a semiconductor fabrication (FAB) process. In one exemplified embodiment, the manufacturing method of the semiconductor device includes preparing a first semiconductor die including a plurality of through electrodes and a plurality of first conductive pillars, mounting the first semiconductor die to connect the first conductive pillars to the pattern layer provided on a wafer, forming a first encapsulant to cover the pattern layer and the first semiconductor die, mounting a second semiconductor die to electrically connect second conductive pillars provided in the second semiconductor die to the plurality of through electrodes exposed to a second surface of the first semiconductor die, and removing the wafer from a first surface of the pattern layer.Type: ApplicationFiled: March 18, 2014Publication date: September 25, 2014Applicant: Amkor Technology, Inc.Inventors: Pil Je Sung, Seong Min Seo, Jong Sik Paek, Seo Yeon Ahn, Hui Tae Kim
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Patent number: 8502361Abstract: In accordance with the present invention, there is provided a CPV package which comprises a leadframe assembly, such leadframe assembly including multiple frames stacked on top of each other. A top frame of the leadframe assembly provides the electrical interconnect between the top or front surface of the receiver die and the bypass diode required to complete the circuit. The top frame also provides hook up wire interconnect pads for the completed CPV package. An exposed bottom surface of a bottom frame of the leadframe assembly defines a heat spreader which assists in thermal management. The fabrication of the CPV package to include multiple frames stacked on top of each other provides high thermal dissipation and high voltage isolation, while at the same providing a high level of reliability with a comparatively low manufacturing cost.Type: GrantFiled: December 9, 2010Date of Patent: August 6, 2013Assignee: Amkor Technology, Inc.Inventors: John M. Nickelsen, Jr., Pil Je Sung, Garry Pycroft