Abstract: A memory array that includes a plurality of memory blocks and a plurality of source switches is introduced. Each of the source switches corresponds to one of the memory blocks, and each of the source switches is coupled to a common source line of the corresponding one of the memory blocks. A selected source switch, which corresponds to a selected memory block among the memory blocks for a program operation, is configured to bias the common source line of the selected memory block to a reference voltage during a program period of the program operation. An unselected source switch, which corresponds to an unselected memory block among the memory blocks for the program operation, is configured to float the common source line of the unselected memory block during the program period of the program operation.

Abstract: A memory circuit and a memory programming method adapted to program flash memory are provided. The memory circuit includes a charge pumping circuit, a voltage regulator, a voltage sensor, and a plurality of switch circuits. The charge pumping circuit generates a pumping voltage and a pumping current. The voltage regulator is coupled to the charge pumping circuit and generates a programming voltage and a programming current to program the flash memory according to the pumping voltage and the pumping current. The voltage sensor is coupled to the voltage regulator to monitor a voltage value of the programming voltage. Each of the plurality of switch circuits includes a first terminal coupled to the voltage sensor and a second terminal coupled to the flash memory. A quantity of the plurality of switch circuits that are turned on is determined by the voltage value of the programming voltage.

Abstract: A memory circuit and a memory programming method adapted to program flash memory are provided. The memory circuit includes a charge pumping circuit, a voltage regulator, a voltage sensor, and a plurality of switch circuits. The charge pumping circuit generates a pumping voltage and a pumping current. The voltage regulator is coupled to the charge pumping circuit and generates a programming voltage and a programming current to program the flash memory according to the pumping voltage and the pumping current. The voltage sensor is coupled to the voltage regulator to monitor a voltage value of the programming voltage. Each of the plurality of switch circuits includes a first terminal coupled to the voltage sensor and a second terminal coupled to the flash memory. A quantity of the plurality of switch circuits that are turned on is determined by the voltage value of the programming voltage.

Abstract: This invention introduces an electronic apparatus and an operative method thereof which are capable of triggering an initialization operation for the electronic apparatus correctly. The electronic apparatus includes a plurality of latches and a power power-on-reset generator. The plurality of latches are coupled to memory cells and are configured to monitor memory data of the memory cells. The power-on-reset generator is coupled to the plurality of latches and is configured to generate a power-on-reset pulse to reset the electronic apparatus in response to a data corruption on at least one of the memory cells. The data corruption is detected during an initialization operation of the electronic apparatus according to memory data of the memory cells and corresponding hardwired code data.

Abstract: A random number generation system and a random number generation method thereof are provided. The random number generation system includes a random number generator, a random number selection circuit, and a random number logic circuit. The random number generator receives the random number request signal to provide a first random number sequence with n bits, where n is a positive integer. The random number selection circuit receives the random number request signal to provide a bit selection signal with n bits, wherein the bit selection signal is a time varying signal and is determined by the received random number request signal. The random number logic circuit receives the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide the second random number sequence.

Abstract: This invention introduces an electronic apparatus and an operative method thereof which are capable of triggering an initialization operation for the electronic apparatus correctly. The electronic apparatus includes a plurality of latches and a power power-on-reset generator. The plurality of latches are coupled to memory cells and are configured to monitor memory data of the memory cells. The power-on-reset generator is coupled to the plurality of latches and is configured to generate a power-on-reset pulse to reset the electronic apparatus in response to a data corruption on at least one of the memory cells. The data corruption is detected during an initialization operation of the electronic apparatus according to memory data of the memory cells and corresponding hardwired code data.

Abstract: A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array, and a memory controller is provided. The memory cell array includes a plurality of memory cells. The memory cells are configured to store data. Each of the memory cells is coupled to the corresponding word line and the corresponding bit line. The memory controller is configured to perform a read operation to the memory cell array. The memory controller performs a pre-charge operation to part or all of the bit lines when the memory controller enables the word lines. In addition, an operating method of a memory storage apparatus is also provided.

Abstract: A random number generating system and a random number generating method thereof are provided. The random number generating system includes a random number generator, a random mask circuit, a bit reduction logic circuit and a receiver. The random number generator provides a random number sequence. The random mask circuit receives the random number sequence to provide a random number mask sequence and a random mask indication sequence, wherein bits of the random mask indication sequence in a first logical level corresponded to bits of the random number mask sequence in the high impedance state. The bit reduction logic circuit receives the random number sequence and the random mask indication sequence to provide the comparison key. The receiver receives a random number mask sequence to provide a verification key, where the verification key is the same as the comparison key.

Abstract: A random number generating system and a random number generating method thereof are provided. The random number generating system includes a random number generator, a random mask circuit, a bit reduction logic circuit and a receiver. The random number generator provides a random number sequence. The random mask circuit receives the random number sequence to provide a random number mask sequence and a random mask indication sequence, wherein bits of the random mask indication sequence in a first logical level corresponded to bits of the random number mask sequence in the high impedance state. The bit reduction logic circuit receives the random number sequence and the random mask indication sequence to provide the comparison key. The receiver receives a random number mask sequence to provide a verification key, where the verification key is the same as the comparison key.

Abstract: A random number generation system and a random number generation method thereof are provided. The random number generation system includes a random number generator, a random number selection circuit, and a random number logic circuit. The random number generator receives the random number request signal to provide a first random number sequence with n bits, where n is a positive integer. The random number selection circuit receives the random number request signal to provide a bit selection signal with n bits, wherein the bit selection signal is a time varying signal and is determined by the received random number request signal. The random number logic circuit receives the random number request signal, the first random number sequence and the bit selection signal, and in response to the random number request signal to adjust the first random number sequence using the bit selection signal to provide the second random number sequence.

Abstract: A memory storage apparatus including a plurality of word lines, a plurality of bit lines, a memory cell array, and a memory controller is provided. The memory cell array includes a plurality of memory cells. The memory cells are configured to store data. Each of the memory cells is coupled to the corresponding word line and the corresponding bit line. The memory controller is configured to perform a read operation to the memory cell array. The memory controller performs a pre-charge operation to part or all of the bit lines when the memory controller enables the word lines. In addition, an operating method of a memory storage apparatus is also provided.

Abstract: A non-volatile semiconductor memory device capable of eliminating influence of bit line (BL) leakage on reading and a reading method thereof. The non-volatile semiconductor memory device includes a memory array, a semiconductor well having a plurality of erase units, and a source switch array having a plurality of source switches. Each of the source switches is coupled to a common source line of one erase unit of the semiconductor well. Only one source switch among the source switches coupled to a selected erase unit among the erase units of the semiconductor well for reading is enabled during a reading operation. Thus, the BL leakage is prevented from affecting the reading operation on memory cells of the memory array, thereby improving the reliability of the non-volatile semiconductor memory device.

Abstract: A drain pump for flash memory is disclosed that includes a unit for generating a variable voltage depending on a number of bits to be programmed; a pump to pump an input voltage thereof; and a regulator to regulate an output voltage of the pump depending on the variable voltage.

Abstract: A drain pump for flash memory is disclosed that includes a means for generating a variable voltage depending on a number of bits to be programmed; a pump to pump an input voltage thereof; and a regulator to regulate an output voltage of the pump depending on the variable voltage.

Abstract: The present invention relates to a bit counter, and a program circuit of a semiconductor device and a program method using the same. Upon a program operation of a word unit, only program data to be programmed among the program data are counted within a pumping period using the bit counter for counting bits of program data. Then, if the number of the bits of the data to be programmed is less than 8, a program operation is performed at a time. Accordingly, a program operation time can be shorten.

Abstract: The present invention relates to a bit counter, and a program circuit of a semiconductor device and a program method using the same. Upon a program operation of a word unit, only program data to be programmed among the program data are counted within a pumping period using the bit counter for counting bits of program data. Then, if the number of the bits of the data to be programmed is less than 8, a program operation is performed at a time. Accordingly, a program operation time can be shorten.