Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on an axis to define a core and an outer circumference. The first electrode includes an uncoated portion at a long side end thereof and exposed out of the separator along a winding axis direction of the electrode assembly. A part of the uncoated portion is bent in a radial direction of the electrode assembly to form a bending surface region that includes overlapping layers of the uncoated portion, and in a partial region of the bending surface region, the number of stacked layers of the uncoated portion is 10 or more in the winding axis direction of the electrode assembly.

Abstract: Structures and related techniques for singulating GaN-on-Si wafers are disclosed. In one aspect, a semiconductor wafer includes a silicon layer, and a gallium nitride (GaN) layer disposed on the silicon layer and defining a plurality of trenches that each extend to the silicon layer. In another aspect, the GaN layer includes one or more gallium nitride layers of different compositions. In yet another aspect, the wafer includes a plurality of dielectric layers disposed on the GaN layer. In yet another aspect, each of the plurality of trenches has a depth that is equal to a sum of a thickness of the GaN layer and a thickness of the plurality of the dielectric layers.

Abstract: Structures and related techniques for control of two-dimensional electron gas (2DEG) charge density in gallium nitride (GaN) devices are disclosed. In one aspect, a GaN device includes a compound semiconductor substrate, a source region formed in the compound semiconductor substrate, a drain region formed in the compound semiconductor substrate and separated from the source region, a 2DEG layer formed in the compound semiconductor substrate and extending between the source region and the drain region, a gate region formed on the compound semiconductor substrate and positioned between the source region and the drain region, and a plurality of isolated charge control structures disposed between the gate region and the drain region.

Abstract: Field plate structures for gallium nitride (GaN) high voltage transistors are disclosed. In one aspect, a transistor includes a GaN substrate, a source region formed on the GaN substrate, a drain region formed on the GaN substrate and separate from the source region, a gate region formed between the source region and the drain region, a pedestal formed on the GaN substrate and positioned between the gate region and the drain region, and a field plate electrically coupled to the source region, where the field plate extends from a proximal region positioned between the source region and the pedestal, towards the drain region, where at least a portion of the field plate overlaps at least a portion of the pedestal.

Abstract: A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (Vth). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.

Abstract: A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (Vth). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.