Patents by Inventor Pilin Liu
Pilin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317545Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Pilin Liu, Feras Eid, Michael Baker, Wenhao Li, Zhaozhi Li
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Publication number: 20230317660Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate having one or more solder structures. A first set of solder structures is located in a peripheral region of the substrate and a second set of solder structures is located in a central region of the substrate. A height of individual ones of the second set of solder structures is greater than a height of individual ones of the first set of solder structures. A die having a first side and a second side includes one or more conductive die pads on the first side, where individual ones of the conductive die pads are on individual ones of the first set solder structures and on individual ones of the second set solder structures. A die backside layer is on the second side of the die.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Zhaozhi Li, Feras Eid, Michael Baker, Wenhao Li, Pilin Liu, Johanna Swan
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Publication number: 20230317676Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) assembly including a bond head with a first thermal zone separated from a second thermal zone by a thermal separator, the thermal separator extending through a thickness of the bond head. A bond head nozzle is coupled to a first side of the bond head, where the bond head nozzle includes one or more nozzle channels extending through a thickness of the bond head nozzle.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Michael Baker, Feras Eid, Wenhao Li, Zhaozhi Li, Pilin Liu
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Publication number: 20230317630Abstract: Microelectronic die package structures formed according to some embodiments may include a substrate comprising one or more conductive interconnect structures on a surface of the substrate. One or more support features are on one or more peripheral regions of the surface of the substrate. A first side of a die is coupled to the one or more conductive interconnect structures and is over the one or more support features. A die backside layer is on the second side of the die.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Wenhao Li, Feras Eid, Michael Baker, Pilin Liu, Zhaozhi Li
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Publication number: 20230317675Abstract: Microelectronic die package structures formed according to some embodiments may include a thermal compression bonding (TCB) tool including a pedestal having a convex surface to receive a package substrate, a bond head to compress a die against the package substrate, and a heat source thermally coupled to at least one of the pedestal or the bond head.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Michael Baker, Zhaozhi Li, Feras Eid, Pilin Liu, Wenhao Li
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Patent number: 11387175Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.Type: GrantFiled: August 9, 2018Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Debendra Mallik, Sanka Ganesan, Pilin Liu, Shawna Liff, Sri Chaitra Chavali, Sandeep Gaan, Jimin Yao, Aastha Uppal
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Publication number: 20200051899Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: Debendra MALLIK, Sanka GANESAN, Pilin LIU, Shawna LIFF, Sri Chaitra CHAVALI, Sandeep GAAN, Jimin YAO, Aastha UPPAL
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Patent number: 10361167Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).Type: GrantFiled: September 25, 2015Date of Patent: July 23, 2019Assignee: Intel CorporationInventors: Pilin Liu, Purushotham Kaushik Muthur Srinath, Deepak Goyal
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Publication number: 20180254256Abstract: Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).Type: ApplicationFiled: September 25, 2015Publication date: September 6, 2018Inventors: Pilin Liu, Purushotham Kaushik Muthur Srinath, Deepak Goyal
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Publication number: 20170059303Abstract: Some example forms relate to a method of nondestructively measuring a geometry of an electrical component on a substrate. The method includes directing light at the electrical component. The light is at an original intensity. The method further includes measuring light that is reflected off of the electrical component. The reflected light includes undiffracted light and diffracted light. The diffracted light is at a diffracted intensity. The method further includes determining a ratio of diffracted intensity to original intensity and utilizing the ratio to determine a geometry of the electrical component.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Robert Alan May, Sri Ranga Sai Boyapati, Zhiyong Wang, Shuhong Liu, Pilin Liu
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Publication number: 20150255414Abstract: Embodiments of the present disclosure describe solder compounds for electrically coupling integrated circuit (IC) substrates as well as methods for using the solder compounds to couple IC subtrates. The solder compounds are formulated with lower Copper (Cu) percentages to prevent the formation of Cu rich intermettalic compounds (IMCs) which may undergo transitions at elevated temperatures resulting in void formation when NiPdAu or NiAu surface finishes are used on both sides of the solder interconnect. Additionally, nickel (Ni), may be included in the solder compounds to improve fatigue and/or creep properties. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 7, 2014Publication date: September 10, 2015Inventors: Pilin Liu, Yan Li, Deepak Goyal
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Patent number: 8759974Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.Type: GrantFiled: August 8, 2011Date of Patent: June 24, 2014Assignee: Intel CorporationInventors: Mengzhi Pang, Pilin Liu, Charavanakumara Gurumurthy
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Publication number: 20110293962Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Inventors: Mengzhi PANG, Pilin LIU, Charan GURUMURTHY
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Patent number: 8013444Abstract: Electronic assemblies and solders used in electronic assemblies are described. One embodiment includes a die and a substrate, with a solder material positioned between the die and the substrate, the solder comprising at least 91 weight percent Sn, 0.4 to 1.0 weight percent Cu and at least one dopant selected from the group consisting of Ag, Bi, P, and Co. Other embodiments are described and claimed.Type: GrantFiled: December 24, 2008Date of Patent: September 6, 2011Assignee: Intel CorporationInventors: Mengzhi Pang, Pilin Liu, Charavanakumara Gurumurthy