Abstract: An integrated circuit device includes a back side interconnection structure extending in a first horizontal direction. An active substrate includes a fin-type active area extending in the first horizontal direction on the back side interconnection structure. A metal silicide film is between the back side interconnection structure and the active substrate. A plurality of gate structures extends in a second horizontal direction perpendicular to the first horizontal direction on the active substrate. A first source/drain area and a second source/drain area are spaced apart from each other in the first horizontal direction with the plurality of gate structures therebetween on the active substrate. The first source/drain area directly contacts the active substrate. The second source/drain area is spaced apart from the active substrate and insulated from the active substrate.

Abstract: A semiconductor device includes an active region, a plurality of channel layers spaced apart from each other on the active region, a gate structure including a gate dielectric layer and a gate electrode, and source/drain regions on both sides of the gate structure. The gate structure includes an upper portion and lower portions. A first lower portion of the lower portions has a first lower surface, a first upper surface, and first and second side surfaces. Each of the first and second side surfaces includes a first inclined portion sloped at a first acute angle from the first lower surface and a second inclined portion sloped at a second acute angle from the first upper surface. The gate dielectric layer includes portions disposed between the gate electrode and the plurality of channel layers and between the gate electrode and the source/drain regions.

Abstract: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.