Abstract: Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.

Abstract: A semiconductor package includes: a lower substrate including a lower wiring layer; a semiconductor chip disposed on the lower substrate, the semiconductor chip including a first surface facing the lower substrate and a second surface opposite to the first surface; an upper substrate disposed on the lower substrate and the semiconductor chip, the upper substrate including a lower surface on which support members protruding toward the second surface of the semiconductor chip are disposed; a connection structure disposed between the lower substrate and the upper substrate; an encapsulant filling a space between the lower substrate and the upper substrate and encapsulating at least a portion of the semiconductor chip and the connection structure; and adhesive members disposed on the second surface of the semiconductor chip such as to correspond to the support members, respectively, the adhesive members disposed in contact with the second surface and the support members.

Abstract: A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface. A semiconductor chip is on the first surface of the substrate. A passive element is on the second surface of the substrate. The substrate includes a first passive element pad and a second passive element pad that are exposed by the second surface. A dam extends downwardly from the second surface. The dam includes a first dam and a second dam. The passive element is disposed between the first dam and the second dam. The passive element includes a first electrode portion electrically connected to the first passive element pad. A second electrode portion is electrically connected to the second passive element pad.

Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposite to the first surface. A semiconductor chip is on the first surface of the substrate. A passive element is on the second surface of the substrate. The substrate includes a first passive element pad and a second passive element pad that are exposed by the second surface. A dam extends downwardly from the second surface. The dam includes a first dam and a second dam. The passive element is disposed between the first dam and the second dam. The passive element includes a first electrode portion electrically connected to the first passive element pad. A second electrode portion is electrically connected to the second passive element pad.