Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and the electronic element is encapsulated by a heat dissipation covering layer, and the heat dissipation covering layer is in contact with a metal layer formed on a side surface of the carrier structure, so that heat around the electronic element can be dissipated quickly to effectively avoid a problem of failure of the electronic element due to overheating during operation.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic structure is tightly bonded to a carrier structure via a bonding layer, and the bonding layer includes a first bonding material and a second bonding material adjacent to the first bonding material, so that the second bonding material can fill in a deformation place of the first bonding material to ensure that no void is formed between the bonding layer and the carrier structure after the bonding layer is bonded to the carrier structure.

Abstract: A three-terminal power line fault location and correction system and method, and a computer readable storage medium. An electronic device is electrically connected with a plurality of terminal devices. When a fault occurs at a certain position of the power line, each terminal device detects the fault to generate a fault distance corresponding to the fault. The electronic device corrects the fault distance as follows: the corrected fault distance of one of the terminal devices=(an actual distance between the terminal device and a divergence point+a function of actual distances between the other two terminal devices and the divergence point)*the fault distance corresponding to the terminal device/(the fault distance corresponding to the terminal device+the fault distance corresponding to a function of the actual distances between the other two terminal devices and the divergence point).

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: A recessed induction cooker with a heat insulation protection pad structure and a temperature detection device includes: a heat insulation protection pad, having at least one through hole; a recessed induction cooker, having a housing, a support, a coil and an arched panel; and a temperature detection module, having a temperature detector, a central processing unit and a circuit controller, wherein the temperature detector is for detecting a temperature of the arched panel to generate a temperature value, the central processing unit has a threshold unit and a comparison unit, the threshold unit pre-stores a temperature threshold, the comparison unit compares the temperature threshold with the temperature value, and the central processing unit drives the circuit controller to control the coil to stop heating when the temperature value is greater than or equal to the temperature threshold.

Abstract: An electronic device is provided, including a substrate, and a plurality of first bonding pads. The substrate includes a bonding area. The plurality of first bonding pads are disposed on the substrate and disposed in the bonding area. A part of the plurality of first bonding pads are arranged along a first direction, and another part of the plurality of first bonding pads are arranged along a second direction. There is an included angle between the first direction and the second direction, and the included angle is greater than 0 degrees and less than 90 degrees.

Abstract: An antenna-in-package construction includes a chip layer, a second dielectric layer, and a first dielectric layer stacked in order. The first dielectric layer has a dielectric constant more than 3.5. The antenna-in-package construction includes a transmitting antenna array, a receiving antenna array, and metal isolated pillars. The transmitting antenna array extends from the chip layer to the first dielectric layer through the second dielectric layer. The receiving antenna array extends from the chip layer to the second dielectric layer. The transmitting antenna array and the receiving antenna array are arranged in an alternating interleaved sequence. The metal isolated pillars surround each transmitting antenna and each receiving antenna. The chip layer includes at least one transmitting chip and at least one receiving chip. The transmitting chip and the receiving chip are electrically connected to the transmitting antenna array and the receiving antenna array, respectively.

Abstract: A kart having a pedal speed controller and other components and arrangements thereof are disclosed. The kart can be provided with a controller for controlling speed; the pedal speed controller comprising a pedestal and a pedal, one end of the pedal is articulated with the pedestal and keeps a certain angle with the pedestal. The pedal speed controller also comprises a sensor connected with the controller, and the sensor can obtain displacement signal along the tread direction of the pedal. The pedal speed controller has the advantages of realizing pedal control of acceleration or deceleration for drivers, avoiding interference with manual adjustment of kart direction, preventing from mutual influence between speed regulation and steering, improving the speed control performance of the kart, and improving the driving experience.

Abstract: An electronic device includes: a substrate; a plurality of electronic components disposed on the substrate, wherein there is a first pitch between two adjacent electronic components in a first direction; and a protective glue disposed on the substrate and the electronic components, and provided with at least one groove disposed between the two adjacent electronic components, wherein a distance between an edge of one of the two adjacent electronic components and the at least one groove satisfies an equation: 0.3 mm ? D ? 1 < ( P / 2 ) , where D1 is the distance between the edge of the one of the two adjacent electronic components and the at least one groove, and P is the first pitch.

Abstract: An electronic device is provided. The electronic device includes: a first substrate, a first light-emitting unit, a wall structure, and a first optical film. The first light-emitting unit is disposed on the first substrate. The wall structure is disposed on the first substrate, and includes a first opening corresponding to the first light-emitting unit. At least a portion of the first optical film is disposed on the first light-emitting unit, and the at least a portion of the first optical film is disposed in the first opening.

Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.

Abstract: A light guide plate includes a light incident surface, a first surface connected to the light incident surface, and a plurality of optical microstructures disposed on the first surface. Each optical microstructure has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction perpendicular to the first direction. The first cross-sectional profile is different from the second cross-sectional profile. The optical microstructures include a plurality of first optical microstructures and a plurality of second optical microstructures. The second cross-sectional profile of each first optical microstructure is different from the second cross-sectional profile of each second optical microstructure. A light source module including the light guide plate projects light into the light incident surface.

Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.

Abstract: A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.

Abstract: A fan module and computing device with the fan module are disclosed. The fan module includes a handle configured to actuate between an operation state and a release state. The handle in the release state allows a user to vertically remove the fan module from its respective fan module slot and away from the bottom panel.

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: A vehicle display device includes a light source module, a light splitting element, first and second polarization reflection modules. The light source module provides a first light beam having a first polarization state and a second light beam having a second polarization state. The light splitting element reflects the first light beam and allows the second light beam to pass through. The first polarization reflection module reflects the first light beam to the light splitting element and converts the first polarization state into the second polarization state. The second polarization reflection module reflects the first and second light beam and convert the second polarization states into third polarization states. The first and second light beam from the second polarization reflection module form a far-field virtual image and a near-field virtual image through the imaging element.

Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.

Abstract: A method (of manufacturing a semiconductor device, a corresponding layout diagram including cells such that, for a subset of the cells, each subject one of the cells (subject cell) in the subset has a neighborhood including first and second neighbor cells on corresponding first and second sides of the subject cell relative to the first direction) includes: for each subject cell in the subset, generating a sidefile which represents neighborhood-specific proximity-effect information; and, for each cell in the subset of the cells, the generating a sidefile including: populating the sidefile with a first neighbor-specific proximity-effect (NSPE) parameter (corresponding to an inter-cell proximity-effect induced by the first neighbor cell) identifying a nearest first transistor of the first neighbor cell; and populating the sidefile with a second NSPE parameter (corresponding to an inter-cell proximity-effect induced by the second neighbor cell) identifying a nearest first transistor of the second neighbor cell.