Patents by Inventor Pin Chen

Pin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250060818
    Abstract: A controller includes a body and a surrounding part. The body has a control area for sending a control signal according to a movement of a thumb of a user. The surrounding part is connected to the body and used to surround and be fixed to a proximal phalange of an index finger of the user. The body is away from a joint between the proximal phalange and a metacarpal bone of the user.
    Type: Application
    Filed: July 3, 2024
    Publication date: February 20, 2025
    Applicant: HTC Corporation
    Inventors: Chang-Hua Wei, Yu-Ling Huang, Pei-Pin Huang, Yen Chun Chen, Tung-Ting Cheng, Reinaldo Yang, Chih-Ting Chen
  • Patent number: 12232258
    Abstract: An electronic device is provided, including a substrate, and a plurality of first bonding pads. The substrate includes a bonding area. The plurality of first bonding pads are disposed on the substrate and disposed in the bonding area. A part of the plurality of first bonding pads are arranged along a first direction, and another part of the plurality of first bonding pads are arranged along a second direction. There is an included angle between the first direction and the second direction, and the included angle is greater than 0 degrees and less than 90 degrees.
    Type: Grant
    Filed: October 6, 2022
    Date of Patent: February 18, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Shang-Ru Wu, Hua-Pin Chen, Shuai Wang, Chien-Hao Kuo
  • Patent number: 12231436
    Abstract: A method for permission management includes: generating a plurality of job roles with different permissions according to organization permission table; generating first permission structure directed graph according to the job roles; selecting one of the job roles in first permission structure directed graph as target job role; generating minimum directed spanning graph in first permission structure directed graph according to target job role; determining whether permission of each of the job roles in first permission structure directed graph matches job of each of the job roles in first permission structure directed graph; and adjusting permission and job of each of the job roles to generate second permission structure directed graph if it is determined that permission of each of the job roles in first permission structure directed graph does not match job of each of the job roles in first permission structure directed graph.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 18, 2025
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Wei-Chao Chen, Ming-Chi Chang, Chih-Pin Wei, Chuo-Jui Wu
  • Publication number: 20250055190
    Abstract: An antenna-in-package construction includes a chip layer, a second dielectric layer, and a first dielectric layer stacked in order. The first dielectric layer has a dielectric constant more than 3.5. The antenna-in-package construction includes a transmitting antenna array, a receiving antenna array, and metal isolated pillars. The transmitting antenna array extends from the chip layer to the first dielectric layer through the second dielectric layer. The receiving antenna array extends from the chip layer to the second dielectric layer. The transmitting antenna array and the receiving antenna array are arranged in an alternating interleaved sequence. The metal isolated pillars surround each transmitting antenna and each receiving antenna. The chip layer includes at least one transmitting chip and at least one receiving chip. The transmitting chip and the receiving chip are electrically connected to the transmitting antenna array and the receiving antenna array, respectively.
    Type: Application
    Filed: September 18, 2023
    Publication date: February 13, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ching-Wen CHIANG, Huan-Ta Chen, Chung-Lien Ho, Chin Pin Chen
  • Publication number: 20250056712
    Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Applicant: Unimicron Technology Corp.
    Inventors: Jun-Rui Huang, Chih-Chiang Lu, Yi-Pin Lin, Ching-Sheng Chen
  • Publication number: 20250054879
    Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Wen Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
  • Patent number: 12225735
    Abstract: A memory device is provided in various embodiments. The memory device, in those embodiments, has an ovonic threshold switching (OTS) selector comprising multiple layers of OTS materials to achieve a low leakage current and as well as relatively low threshold voltage for the OTS selector. The multiple layers can have at least one layer of low bandgap OTS material and at least one layer of high bandgap OTS material.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: February 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ju Li, Kuo-Pin Chang, Yu-Wei Ting, Ching-En Chen, Kuo-Ching Huang
  • Publication number: 20250042237
    Abstract: A kart having a pedal speed controller and other components and arrangements thereof are disclosed. The kart can be provided with a controller for controlling speed; the pedal speed controller comprising a pedestal and a pedal, one end of the pedal is articulated with the pedestal and keeps a certain angle with the pedestal. The pedal speed controller also comprises a sensor connected with the controller, and the sensor can obtain displacement signal along the tread direction of the pedal. The pedal speed controller has the advantages of realizing pedal control of acceleration or deceleration for drivers, avoiding interference with manual adjustment of kart direction, preventing from mutual influence between speed regulation and steering, improving the speed control performance of the kart, and improving the driving experience.
    Type: Application
    Filed: August 9, 2024
    Publication date: February 6, 2025
    Inventors: Robert (Wei-Pin) Chen, Tony Wang
  • Publication number: 20250046667
    Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 6, 2025
    Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Chih-Pin Chiu, Hsin-Feng Chen, Yu-Bey Wu, Liang-Wei Wang, Dian-Hau Chen
  • Patent number: 12216326
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 4, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiang-Chin Lin, Shou-Jen Liu, Guan-Bo Wang, Kai-Po Fan, Chan-Jung Hsu, Shao-Chung Chang, Shih-Wei Hung, Ming-Chun Hsieh, Wei-Pin Chin, Sheng-Zong Chen, Yu-Huai Liao, Sin-Hong Lin, Wei-Jhe Shen, Tzu-Yu Chang, Kun-Shih Lin, Che-Hsiang Chiu, Sin-Jhong Song
  • Patent number: 12215422
    Abstract: A shower head structure and a plasma processing apparatus are provided. The shower head structure includes a plate body with a first zone and a second zone on a first surface. A plurality of first through holes are in the first zone, each of the first through holes having a diameter uniform with others of the first through holes. A plurality of second through holes are in the second zone. The first zone is in connection with the second zone, and the diameter of each of the first through holes is greater than a diameter of each of the second through holes. A plasma processing apparatus includes the shower head structure is also provided.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Huan-Chieh Chen, Jhih-Ren Lin, Tai-Pin Liu, Shyue-Shin Tsai, Keith Kuang-Kuo Koai
  • Publication number: 20250040318
    Abstract: An electronic device includes: a substrate; a plurality of electronic components disposed on the substrate, wherein there is a first pitch between two adjacent electronic components in a first direction; and a protective glue disposed on the substrate and the electronic components, and provided with at least one groove disposed between the two adjacent electronic components, wherein a distance between an edge of one of the two adjacent electronic components and the at least one groove satisfies an equation: 0.3 mm ? D ? 1 < ( P / 2 ) , where D1 is the distance between the edge of the one of the two adjacent electronic components and the at least one groove, and P is the first pitch.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 30, 2025
    Inventors: Zhi-Wei ZHANG, Hua-Pin CHEN, Shuai WANG, Chien-Hao KUO
  • Publication number: 20250040323
    Abstract: An electronic device is provided. The electronic device includes: a first substrate, a first light-emitting unit, a wall structure, and a first optical film. The first light-emitting unit is disposed on the first substrate. The wall structure is disposed on the first substrate, and includes a first opening corresponding to the first light-emitting unit. At least a portion of the first optical film is disposed on the first light-emitting unit, and the at least a portion of the first optical film is disposed in the first opening.
    Type: Application
    Filed: June 24, 2024
    Publication date: January 30, 2025
    Inventors: Yu-Ding LIN, Hua-Pin CHEN, Shuai WANG, Chien-Hao KUO
  • Publication number: 20250038998
    Abstract: The present invention relates to a cyber security authentication method. The method includes the following steps: in a user device: randomly generating an ephemeral decryption key, transmitting the ephemeral decryption key to a security server, and retrieving a key index from the security server; encrypting an identity information based on a part of the ephemeral decryption key to generate an electronic digital signature and an authentication token; and combining the key index, the electronic digital signature, and the authentication token to form an ephemeral certificate and transmitting the ephemeral certificate to a non-Internet electronic device; and in the non-Internet electronic device: parsing the ephemeral certificate to obtain the key index; and forwarding the key index to the security server via a transport connection including the user device to retrieve the ephemeral decryption key from the security server based on the key index.
    Type: Application
    Filed: May 30, 2024
    Publication date: January 30, 2025
    Inventors: Jia-You JIANG, Tsu-Pin WENG, Yuan-Sheng CHEN, Jung-Hua LO, Yin-Te Tsai, Wen-Hsing KUO, Ming-Feng LU
  • Patent number: 12209867
    Abstract: A spherical multi-axis optical fiber sensing device is formed by a three-axis optical interference sensor composed of a multi-level opto-mechanical integrated unit kit. The opto-mechanical integrated unit kit is composed of three fiber rings, which are respectively a large fiber ring, a medium fiber ring and a small fiber ring. The multi-level opto-mechanical integrated unit kit is combined with the use of the mechanism component technology that can be freely rotated and positioned to achieve the functional purpose of establishing a three-axis orthogonal optical fiber sensing unit in a single sphere volume.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 28, 2025
    Assignee: AEGIVERSE CO., LTD
    Inventors: Hung-Pin Chung, Ching-Lu Hsieh, Sheng-Han Chang, Chii-Chang Chen, Yen-Hung Chen, Jann-Yenq Liu
  • Patent number: 12204450
    Abstract: A computing system performs shared cache allocation to allocate cache resources to groups of tasks. The computing system monitors the bandwidth at a memory hierarchy device that is at a next level to the cache in a memory hierarchy of the computing system. The computing system estimates a change in dynamic power from a corresponding change in the bandwidth before and after the cache resources are allocated. The allocation of the cache resources are adjusted according to an allocation policy that receives inputs including the estimated change in the dynamic power and a performance indication of task execution.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: January 21, 2025
    Assignee: MediaTek Inc.
    Inventors: Yu-Pin Chen, Jia-Ming Chen, Chien-Yuan Lai, Ya Ting Chang, Cheng-Tse Chen
  • Publication number: 20250022931
    Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.
    Type: Application
    Filed: July 22, 2024
    Publication date: January 16, 2025
    Inventors: Ting-Yeh CHEN, Wei-Yang LEE, Chia-Pin LIN, Da-Wen LIN
  • Publication number: 20250020852
    Abstract: A light guide plate includes a light incident surface, a first surface connected to the light incident surface, and a plurality of optical microstructures disposed on the first surface. Each optical microstructure has a first cross-sectional profile along a first direction and a second cross-sectional profile along a second direction perpendicular to the first direction. The first cross-sectional profile is different from the second cross-sectional profile. The optical microstructures include a plurality of first optical microstructures and a plurality of second optical microstructures. The second cross-sectional profile of each first optical microstructure is different from the second cross-sectional profile of each second optical microstructure. A light source module including the light guide plate projects light into the light incident surface.
    Type: Application
    Filed: March 8, 2024
    Publication date: January 16, 2025
    Applicant: CM Visual Technology Corporation
    Inventors: Tsang-Chi Wang, Hsin Wen Chang, Hung Yu Lin, Yung Pin Chen
  • Patent number: 12183593
    Abstract: A manufacturing method for manufacturing a package structure is provided. The manufacturing method includes: (a) providing a carrier having a top surface and a lateral side surface, wherein the top surface includes a main portion and a flat portion connecting the lateral side surface, and a first included angle between the main portion and the flat portion is less than a second included angle between the main portion and the lateral side surface; (b) forming an under layer on the carrier to at least partially expose the flat portion; and (c) forming a dielectric layer on the under layer and covering the exposed flat portion.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 31, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Pin Chen, Chia Sheng Tien, Wan-Ting Chiu, Chi Long Tsai, Cyuan-Hong Shih, Yen Liang Chen
  • Publication number: 20240429310
    Abstract: A semiconductor device may include a electrostatic discharge (ESD) protection circuit and a high voltage ESD triggering circuit that is configured to trigger ESD protection for high voltage circuits of the semiconductor device. The high voltage ESD triggering circuit may be implemented by one or more of the example implementations of high voltage ESD triggering circuits described herein. The example implementations of high voltage ESD triggering circuits described herein are capable of handle high voltages of the high voltage circuits included in the semiconductor device. This reduces the likelihood of and/or prevents premature triggering of ESD protection during normal operation for these high voltage circuits, and enables the high voltage circuits to be protected from high voltage ESD events.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Sheng-Fu HSU, Shih-Fan CHEN, Chen-Yi LEE, Pin-Chen CHEN, Lin-Yu HUANG