Abstract: A three-terminal power line fault location and correction system and method, and a computer readable storage medium. An electronic device is electrically connected with a plurality of terminal devices. When a fault occurs at a certain position of the power line, each terminal device detects the fault to generate a fault distance corresponding to the fault. The electronic device corrects the fault distance as follows: the corrected fault distance of one of the terminal devices=(an actual distance between the terminal device and a divergence point+a function of actual distances between the other two terminal devices and the divergence point)*the fault distance corresponding to the terminal device/(the fault distance corresponding to the terminal device+the fault distance corresponding to a function of the actual distances between the other two terminal devices and the divergence point).

Abstract: A semiconductor package includes a semiconductor die, an interposer disposed below the semiconductor die, first joints electrically coupling the semiconductor die to the interposer, at least one second joint coupling the semiconductor die to the interposer, and a first underfill disposed between the semiconductor die and the interposer to surround the active and second joints. The semiconductor die includes a first region, a seal ring region surrounding the first region, and a second region between the seal ring region and a die edge. The first joints are located within the first region, and the second joint is disposed at a die corner within the second region and is electrically floating in the semiconductor package.

Abstract: An antenna structure and an electronic device are provided. The antenna structure includes a feeding source, a main radiation portion, a metal portion, and a grounding portion. The main radiation portion is signally connected to the feeding source. There is a first gap between the metal portion and the main radiation portion. There is a second gap between the grounding portion and the metal portion, and there is a third gap between the grounding portion and the main radiation portion. The main radiation portion couples with the metal portion via the first gap, and the grounding portion couples with the metal portion via the second gap.

Abstract: A method for recognizing different object-categories within images based on texture classification of the different categories, which is implemented in an electronic device, includes extracting texture features from block images segmented from original images according to at least one Gabor filter; determining a grayscale level co-occurrence matrix of each block image according to the texture features; calculating texture feature statistics of each block image according to the grayscale level co-occurrence matrix; training and generating an object recognition model using the texture features and the texture feature statistics; and recognizing and classifying at least one object in original image according to the object recognition model.

Abstract: An image sensor module includes a sensing surface, a filter element and a first anti-reflective microstructure, wherein the filter element faces towards the sensing surface, and the first anti-reflective microstructure is disposed on the sensing surface. The filter element includes a substrate, an optical deposition layer structure and an optical coating layer, wherein the optical deposition layer structure is disposed on a side of the substrate away from the sensing surface, and the optical coating layer and the optical deposition layer structure are correspondingly disposed on a side of the substrate facing towards the sensing surface. The optical deposition layer structure is multilayer. An air layer is formed between the first anti-reflective microstructure and the filter element, and the first anti-reflective microstructure and the air layer partially overlap at a direction vertical to the sensing surface.

Abstract: An electronic device includes: a substrate, a poly-silicon layer disposed on the substrate, a first metal layer disposed on the substrate, a first insulating layer disposed on the first metal layer, a second insulating layer disposed on the first insulating layer; and a second metal layer covering a part of the second insulating layer and electrically connected to the first metal layer. Wherein a thickness of the second insulating layer under the second metal layer is larger than a thickness of the second insulating layer uncovered with the second metal layer.

Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.

Abstract: A device for detecting a wearing status of a headphone includes a sensor, a player, an acoustic detection assembly and a microprocessor, where the acoustic detection assembly is connected to the player through a digital-to-analog converter, and the microprocessor is connected to the sensor and the acoustic detection assembly separately; the sensor is configured to determine, in combination with the microprocessor, a wearing status of the headphone within a period of time after current time in the case where the headphone is in a worn status at the current time; and the acoustic detection assembly is configured to determine, in combination with the microprocessor and the player, the wearing status of the headphone within the period of time after the current time in the case where the headphone is in a non-worn status at the current time.

Abstract: A recessed induction cooker with a heat insulation protection pad structure and a temperature detection device includes: a heat insulation protection pad, having at least one through hole; a recessed induction cooker, having a housing, a support, a coil and an arched panel; and a temperature detection module, having a temperature detector, a central processing unit and a circuit controller, wherein the temperature detector is for detecting a temperature of the arched panel to generate a temperature value, the central processing unit has a threshold unit and a comparison unit, the threshold unit pre-stores a temperature threshold, the comparison unit compares the temperature threshold with the temperature value, and the central processing unit drives the circuit controller to control the coil to stop heating when the temperature value is greater than or equal to the temperature threshold.

Abstract: A light guide assembly includes a housing element, at least one light guide element, and at least one light-shielding element. The housing element includes an outer surface and an inner surface. The light guide element is configured for a light to pass therethrough. The light guide element includes a light entrance surface, at least one light exit surface, and at least one wall surface. The wall surface surrounds and is connected to an edge of the light exit surface and extends toward the light entrance surface. The light exit surface is in contact with the inner surface. The at least one light-shielding element surrounds the at least one wall surface and is in contact with the inner surface.

Abstract: Provided are an intelligent call noise reduction device, method, and headphone. The device includes a first microphone, a second microphone, a sound collecting and processing module and a loudspeaker unit. The first microphone is near to a primary talker sound source. The second microphone is near to a third-party talker sound source. The first microphone receives a talker sound source and generates a first voltage signal based on the talker sound source and receives a background sound source and generates a second voltage signal based on the background sound source. The second microphone receives the talker sound source and generates a third voltage signal based on the talker sound source and receives the background sound source and generates 10 a fourth voltage signal based on the background sound source. The talker sound source includes the primary talker sound source and the third-party talker sound source.

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

Abstract: A data processing method applied in a data center is provided.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A controller includes a body and a surrounding part. The body has a control area for sending a control signal according to a movement of a thumb of a user. The surrounding part is connected to the body and used to surround and be fixed to a proximal phalange of an index finger of the user. The body is away from a joint between the proximal phalange and a metacarpal bone of the user.

Abstract: An electronic device is provided, including a substrate, and a plurality of first bonding pads. The substrate includes a bonding area. The plurality of first bonding pads are disposed on the substrate and disposed in the bonding area. A part of the plurality of first bonding pads are arranged along a first direction, and another part of the plurality of first bonding pads are arranged along a second direction. There is an included angle between the first direction and the second direction, and the included angle is greater than 0 degrees and less than 90 degrees.

Abstract: A method for permission management includes: generating a plurality of job roles with different permissions according to organization permission table; generating first permission structure directed graph according to the job roles; selecting one of the job roles in first permission structure directed graph as target job role; generating minimum directed spanning graph in first permission structure directed graph according to target job role; determining whether permission of each of the job roles in first permission structure directed graph matches job of each of the job roles in first permission structure directed graph; and adjusting permission and job of each of the job roles to generate second permission structure directed graph if it is determined that permission of each of the job roles in first permission structure directed graph does not match job of each of the job roles in first permission structure directed graph.

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

Abstract: An antenna-in-package construction includes a chip layer, a second dielectric layer, and a first dielectric layer stacked in order. The first dielectric layer has a dielectric constant more than 3.5. The antenna-in-package construction includes a transmitting antenna array, a receiving antenna array, and metal isolated pillars. The transmitting antenna array extends from the chip layer to the first dielectric layer through the second dielectric layer. The receiving antenna array extends from the chip layer to the second dielectric layer. The transmitting antenna array and the receiving antenna array are arranged in an alternating interleaved sequence. The metal isolated pillars surround each transmitting antenna and each receiving antenna. The chip layer includes at least one transmitting chip and at least one receiving chip. The transmitting chip and the receiving chip are electrically connected to the transmitting antenna array and the receiving antenna array, respectively.

Abstract: A manufacturing method of the circuit board includes the following. The third substrate has an opening and includes a first, a second and a third dielectric layers. The opening penetrates the first and the second dielectric layers, and the opening is fully filled with the third dielectric layer. The first, the second and the third substrates are press-fitted so that the second substrate is located between the first and the third substrates. Multiple conductive structures are formed so that the first, the second and the third substrates are electrically connected through the conductive structures to define a ground path. A conductive via structure is formed to penetrate the first substrate, the second substrate, and the third dielectric layer of the third substrate. The conductive via structure is electrically connected to the first and the third substrates to define a signal path. The ground path surrounds the signal path.