Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

Abstract: The present disclosure relates to magnetic memory device. The magnetic memory device includes a bottom electrode, a selector layer disposed over the bottom electrode, and a MTJ stack disposed over the selector layer and comprising a reference layer and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further includes a modulating layer disposed over the MTJ stack and a top electrode disposed over the switching threshold modulating layer. The selector layer is configured to switch current on and off based on applied bias.

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, and recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins. The method further includes recessing the semiconductor fins to form recesses, epitaxially growing a first semiconductor material from the recesses, etching the first semiconductor material, and epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a surface, and an interlayer dielectric (ILD) defining a metal gate over the surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a capping layer, and a work function metal layer. A thickness of the capping layer sidewall distal to a corner of the capping layer, is substantially thinner than a thickness which is around center of the capping layer bottom. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate recess, forming a high-k dielectric layer, forming a first capping layer, forming a second capping layer on the first capping layer, removing or thinning down the first capping layer sidewall, and removing the second capping layer.

Abstract: According to an exemplary embodiment, a method of forming a MIM capacitor is provided. The method includes the following operations: providing a first metal layer; providing a dielectric layer over the first metal layer; providing a second metal layer over the dielectric layer; etching the second metal layer to define the metal-insulator-metal capacitor; and oxidizing a sidewall of the second metal layer. According to an exemplary embodiment, a MIM capacitor is provided. The MIM capacitor includes a first metal layer; a dielectric layer over the first metal layer; a second metal layer over the dielectric layer; and an oxidized portion in proximity to the second metal layer and made of oxidized second metal layer.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.

Abstract: The present disclosure provides a semiconductor structure includes a semiconductor layer having a surface, and an interlayer dielectric (ILD) defining a metal gate over the surface of the semiconductor layer. The metal gate includes a high-k dielectric layer, a capping layer, and a work function metal layer. A thickness of the capping layer sidewall distal to a corner of the capping layer, is substantially thinner than a thickness which is around center of the capping layer bottom. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate recess, forming a high-k dielectric layer, forming a first capping layer, forming a second capping layer on the first capping layer, removing or thinning down the first capping layer sidewall, and removing the second capping layer.

Abstract: Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.

Abstract: According to an exemplary embodiment, a method of forming a MIM capacitor is provided. The method includes the following operations: providing a first metal layer; providing a dielectric layer over the first metal layer; providing a second metal layer over the dielectric layer; etching the second metal layer to define the metal-insulator-metal capacitor; and oxidizing a sidewall of the second metal layer. According to an exemplary embodiment, a MIM capacitor is provided. The MIM capacitor includes a first metal layer; a dielectric layer over the first metal layer; a second metal layer over the dielectric layer; and an oxidized portion in proximity to the second metal layer and made of oxidized second metal layer.