Patents by Inventor Pin-Chieh Huang
Pin-Chieh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162082Abstract: A manufacturing method of a semiconductor structure including following steps is provided. A first sacrificial layer and a second sacrificial layer are formed in a first substrate. A first device layer including a first dielectric structure and a first landing pad is formed on the first substrate. A second device layer including a second dielectric structure and a second landing pad is formed on a second substrate. The first dielectric structure is bonded to the second dielectric structure. A portion of the first substrate is removed to expose the first sacrificial layer and the second sacrificial layer. An etch-back process is performed by using the first substrate as a mask to form a first opening exposing the first landing pad and a second opening exposing the second landing pad. A first TSV structure and a second TSV structure are respectively formed in the first opening and the second opening.Type: ApplicationFiled: January 6, 2023Publication date: May 16, 2024Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Shyng-Yeuan Che, Ya-Ting Chen, Pin-Chieh Huang
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Publication number: 20240109230Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.Type: ApplicationFiled: May 16, 2023Publication date: April 4, 2024Applicants: Acer Incorporated, Nan Pao New Materials (Huaian) Co., Ltd.Inventors: Pin-Chueh Lin, Wen-Chieh Tai, Cheng-Nan Ling, Chang-Huang Huang
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Publication number: 20240048681Abstract: In one embodiment, a computing system may receive a target image to be displayed on a display. The target image may have a first number of bits per color. The system may access a mask for each color channel of RGB color channels. The accessed masks may be generated based on (1) one or more characteristics of a human visual system, and (2) a subpixel geometry layout of the display. The system may generate an output image based on the target image and the accessed masks. The output image may have a second number of bits per color smaller than the first number of bits per color. The system may display the output image on the display for representing the target image.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Inventors: Pin-Chieh Huang, Edward Buckley
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Publication number: 20230395527Abstract: A semiconductor structure including a substrate, a through-substrate via (TSV), a first insulating layer, an isolation structure, and a capacitor is provided. The substrate includes a TSV region and a keep-out zone (KOZ) adjacent to each other. The TSV is located in the substrate in the TSV region. The first insulating layer is located between the TSV and the substrate. The isolation structure is located in the substrate in the KOZ. There are trenches in the isolation structure. A capacitor is located on the isolation structure and in the trenches.Type: ApplicationFiled: July 6, 2022Publication date: December 7, 2023Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Bo-An Tsai, Pin-Chieh Huang
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Patent number: 11715669Abstract: A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.Type: GrantFiled: August 4, 2021Date of Patent: August 1, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Tse-Hsien Wu, Pin-Chieh Huang, Yu-Hsiang Chien, Yeh-Yu Chiang
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Patent number: 11551636Abstract: In one embodiment, a computing system may determine a group of subpixels, that are associated with different color channels, within a display region of a display. The system may determine a micro-pixel corresponding to a basic unit shape configured to evenly divide the display region and each subpixel. The system may represent the display region as a group of micro-pixels and each subpixel as a combination of one or more micro-pixels in the group of micro-pixels. The system may determine a constraint for each color channel of the display region based on the group of micro-pixels. The constraint may constrain the micro-pixels associated with a same subpixel to have a same color value. The system may generate, based on an optimization process using the constraint, a filter for the display region. The filter may be configured to adjust image pixel values to be displayed by the group of subpixels.Type: GrantFiled: December 21, 2020Date of Patent: January 10, 2023Assignee: Meta Platforms Technologies, LLCInventors: Edward Buckley, Pin-Chieh Huang
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Patent number: 11527564Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.Type: GrantFiled: January 11, 2021Date of Patent: December 13, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
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Publication number: 20220130725Abstract: A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.Type: ApplicationFiled: August 4, 2021Publication date: April 28, 2022Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Tse-Hsien Wu, Pin-Chieh Huang, Yu-Hsiang Chien, Yeh-Yu Chiang
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Publication number: 20210134864Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.Type: ApplicationFiled: January 11, 2021Publication date: May 6, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
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Patent number: 10937819Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.Type: GrantFiled: November 8, 2018Date of Patent: March 2, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
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Publication number: 20200075648Abstract: An image sensor including a substrate, a light sensing device, a storage node, a buried gate structure, and a first light shielding layer is provided. The light sensing device is disposed in the substrate. The storage node is disposed in the substrate. The storage node and the light sensing device are separated from each other. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. The first light shielding layer is disposed on the buried gate and is located above the storage node. The first light shielding layer is electrically connected to the buried gate.Type: ApplicationFiled: November 8, 2018Publication date: March 5, 2020Applicant: Powerchip Technology CorporationInventors: Shih-Ping Lee, Pin-Chieh Huang, Jui-Hung Hung, Yi-Chen Yeh, Cheng-Han Yang, Wen-Hao Huang
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Patent number: 8671289Abstract: In one aspect, a multi-port interface circuit applied to a playback apparatus which is able to switch among a plurality of input ports coupled to a plurality of source devices for playing back. Each input port has a receiver, the receiver including a front-end for receiving and processing a data stream from the source device and providing a data enable signal, and further including a content protection circuit for performing content protection according to the data enable signal. Each receiver records data enable information associated with the data enable signal of the data stream in an initial status. When one input port is selected, receivers of the other input ports operate in a power saving mode, the front-end circuits stop receiving the data stream, and the content protection circuit maintains operation according to a regenerated enable signal, which is regenerated according to the data enable information.Type: GrantFiled: June 2, 2011Date of Patent: March 11, 2014Assignee: MStar Semiconductor, Inc.Inventors: Jin-Chyuan Fuh, Pin-Chieh Huang, Shu-Rung Li
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Publication number: 20120054517Abstract: In one aspect, a multi-port interface circuit applied to a playback apparatus which is able to switch among a plurality of input ports coupled to a plurality of source devices for playing back. Each input port has a receiver, the receiver including a front-end for receiving and processing a data stream from the source device and providing a data enable signal, and further including a content protection circuit for performing content protection according to the data enable signal. Each receiver records data enable information associated with the data enable signal of the data stream in an initial status. When one input port is selected, receivers of the other input ports operate in a power saving mode, the front-end circuits stop receiving the data stream, and the content protection circuit maintains operation according to a regenerated enable signal, which is regenerated according to the data enable information.Type: ApplicationFiled: June 2, 2011Publication date: March 1, 2012Applicant: MSTAR SEMICONDUCTOR, INC.Inventors: Jin-Chyuan Fuh, Pin-Chieh Huang, Shu-Rung Li