Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: Provided is a semiconductor device includes a gate electrode, a gate dielectric layer, a channel layer, an insulating layer, a first source/drain electrode and a second source/drain electrode, a second dielectric layer, and a stop segment. The gate electrode is located within a first dielectric layer that overlies a substrate. The gate dielectric layer is located over the gate electrode. The channel layer is located on the gate dielectric layer. The insulating layer is located over the channel layer. The first source/drain electrode and the second source/drain electrode are located in the insulating layer, and connected to the channel layer. The second dielectric layer is beside one of the first source/drain electrode and the second source/drain electrode. The stop segment is embedded in the second dielectric layer.

Abstract: A detection device, including a substrate, a gate line, a gate line driving circuit, and a photoelectric element, is provided. The substrate includes a detection area and a peripheral area surrounding the detection area. The gate line is disposed on the substrate and extends from the detection area to the peripheral area. The gate line driving circuit is disposed in the peripheral area of the substrate and includes a first transistor and a second transistor. The first transistor is coupled to a first clock signal and the gate line. The second transistor is coupled to a second clock signal and the first transistor. The photoelectric element is disposed in the detection area and is coupled to the gate line. A distance between the second transistor and the detection area is less than a distance between the first transistor and the detection area.