Abstract: A method and apparatus for calibrating a pipelined analog-to-digital converter (ADC) is disclosed. A method includes reading a first output level from a first sub-ADC, reading one or more additional output levels from one or more additional sub-ADCs, combining the one or more additional output levels from the one or more additional sub-ADCs into a combined output level, and adjusting a comparator threshold of the first sub-ADC when the first output level and the combined output level meet a set of predetermined conditions.

Abstract: A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.

Abstract: Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.

Abstract: Method and apparatus for fast phase locked loop (PLL) settling with reduced frequency overshoot are provided. During acquisition, a first phase offset signal configured to drive a phase error signal to zero is provided at a first circuit of the PLL. The first circuit may be a time-to-digital converter (TDC) of the PLL. A second phase offset signal configured to offset the first phase offset signal is provided at a second circuit of the PLL. The second circuit of the PLL may be a loop filter at the PLL.

Abstract: The problem with duty-cycle correction circuits used by conventional frequency doublers is that they typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

Abstract: The problem with duty-cycle correction circuits used by conventional frequency doubters is that they are typically analog solutions, such as variable delay lines with long chains of inverters or buffers, that directly adjust the reference signal used by a phase-locked loop (PLL). These solutions can considerably increase the noise (e.g., thermal noise and supply noise) of the reference signal, as well as the overall power consumption and cost of the PLL. Rather than directly correct the duty-cycle of the reference signal, the present disclosure is directed to an apparatus and method for measuring the period error between adjacent cycles of a frequency doubled reference signal in terms of cycles of the output signal generated by the PLL (or some other higher frequency signal) and adjusting the division factor of the PLL frequency divider to compensate for the measured period error.

Abstract: An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.

Abstract: An apparatus may comprise a time-to-digital circuit architecture. Other embodiments are described and claimed.