Abstract: A color filter substrate and a display panel are provided. The color filter substrate includes a substrate, first spacers, second spacers, color resist patterns, and at least one dummy-color resist pattern. A first area has a first projection area A. A second area has a second projection area B. The color resist patterns are disposed at least partially around of at least one of the first spacers. A covering area of the color resist patterns in the first area is a. (a/A)*100% is defined as a first coverage rate M. The dummy-color resist pattern is disposed at least partially around of at least one of the second spacers. The covering area of the dummy-color resist pattern in the second area is b. (b/B)*100% is defined as a second coverage rate N. The first projected area A is equal to the second projected area B and 27% ?, (N-M)?58%.

Abstract: A pixel structure includes a plurality of sub-pixels. Each of the sub-pixels includes a first light-emitting diode (LED) and a second LED. The first LED is configured to emit a first color light. The second LED is configured to emit a second color light. Each of the first LED and the second LED includes an anode and a cathode. The anode of the first LED and the anode of the second LED are coupled to a same signal line. The cathode of the first LED and the cathode of the second LED are coupled to different signal lines.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: The present invention proposes a self-emission type display and a repairing method thereof. The self-emission type display includes a carrier substrate and a light-emitting element. The carrier substrate includes a first electrode, a second electrode, and a plurality of repairing electrodes. The first electrode has a plurality of first strip portions connected to a first level. The second electrode has a plurality of second strip portions connected to a second level. The first electrode is separated from the second electrode, and the first level is different from the second level. The repairing electrodes are electrically insulated from the first electrode and the second electrode. The light-emitting element is disposed on the carrier substrate and has a first connecting portion and a second connecting portion. The first connecting portion is electrically connected to the first level through the first strip portions.

Abstract: A display device of the present invention includes a light source layer and a sensing unit layer. The light source layer has a display side and a sensing side at the backside of the display side. The light source layer includes a plurality of first light sources generating a first light, and a plurality of second light sources generating a second light. The first light at least partially emits toward the sensing side; the second light at least partially emits toward the display side. A second wavelength of the second light is different from a first wavelength of the first light. The sensing unit layer is disposed at the sensing side of the light source layer. In a sensing mode, the plurality of the first light sources is activated to generate and provide the first light for the sensing unit layer. In a displaying mode, the plurality of the second light sources is activated to generate the second light for displaying an image at the display side.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: A method for repairing a display panel includes the following steps. A display panel is provided. The display panel includes a substrate and a plurality of pixel units. The pixel units are disposed on the substrate, wherein each pixel unit includes at least one bonding pad, at least one light-emitting device and at least one first substitutive bonding pad. The bonding pad is disposed on the substrate. The light-emitting unit is disposed on the bonding pad and is electrically connected to the bonding pad. The first substitutive bonding pad is disposed on the substrate. A defect detecting process is performed to detect whether the light-emitting device of each pixel unit is defective or not. A repairing process is performed to form a first substitutive light-emitting device on the first substitutive bonding pad when a light-emitting device of a pixel unit is found defective.

Abstract: A pixel structure includes a plurality of sub-pixels. Each of the sub-pixels includes a first light-emitting diode (LED) and a second LED. The first LED is configured to emit a first color light. The second LED is configured to emit a second color light. Each of the first LED and the second LED includes an anode and a cathode. The anode of the first LED and the anode of the second LED are coupled to a same signal line. The cathode of the first LED and the cathode of the second LED are coupled to different signal lines.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

Abstract: A pixel structure includes a substrate, a scan line on the substrate, a data line set, an active device, and a pixel electrode. The substrate has a display region and a peripheral region around the display region. The display region includes at least one sub-pixel region. The data line set is disposed on the substrate, located at one side of the sub-pixel region, and intersected with the scan line to form at least one first intersecting region. The data line set includes a first and a second data lines that are intersected to form at least one second intersecting region. The first and the second data lines are electrically insulated. The active device electrically connects the scan line and to the first data line or the second data line in the data line set. The pixel electrode is located in the sub-pixel region and electrically connects the active device.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.

Abstract: A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect.

Abstract: A driving method for determining target transmittance of a liquid crystal sub-pixel is provided. The liquid crystal sub-pixel has display regions, the liquid crystal sub-pixel displays the target transmittance when liquid crystal voltage applied to each display region is equal to one other and transmittance variation of liquid crystal layer in the liquid crystal sub-pixel is S0 when variation of LC voltage ?VLC occurs. The driving method includes selecting LC voltages in accordance with the target transmittance and area ratio of each display region; and applying each LC voltage to one of the display regions correspondingly, wherein transmittance of each display region is different from the target transmittance, the target transmittance is equal to sum of product of area ratio and transmittance of each display region, and transmittance variation of the liquid crystal layer in the liquid crystal sub-pixel is lower than S0 when variation of LC voltage ?VLC occurs.

Abstract: An active array substrate, an electrode substrate, and a liquid crystal display panel (LCD) are provided. The LCD includes an active array substrate, an electrode substrate, and a liquid crystal layer. The active array substrate includes a base, a plurality of scan lines and data lines disposed on the base, a plurality of pixel electrodes, and a plurality of active devices. Each of the active devices is electrically connected to the corresponding scan line, date line, and pixel electrode to define a pixel region and a non-display region. The electrode substrate includes a base and a common electrode disposed on the base of the electrode substrate. The liquid crystal layer is formed between the active array substrate and the electrode substrate and includes liquid molecules with a threshold voltage, a saturation voltage and ions located in the non-display region.

Abstract: A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect.

Abstract: A driving method with reducing image sticking effect is disclosed. The driving method includes applying a voltage on the data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect, and applying different asymmetric waveforms to different data lines for trapping impurities crossing the data lines and lowering the degree of the image sticking effect.