Patents by Inventor Pin-Ting Liu

Pin-Ting Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7456043
    Abstract: A substrate is provided and a plurality of trenches are formed in the front surface of the substrate. Then, a thermal oxide layer is formed on inner walls of the trenches and the front surface of the substrate. Subsequently, a first structural layer is formed on the thermal oxide layer, dopants are implanted into the first structural layer, a second structural layer is formed on the first structural layer, and an annealing process is performed to reduce the stress of the first and second structural layers. Following that, the first and second structural layers are patterned to form diaphragms. Finally, the second structural layer is mounted on a support wafer with a bonding layer, and the back surface of the substrate is etched by deep etching techniques to form back chambers corresponding to the diaphragms. Each back chamber has a vertical sidewall and partially exposes the first structural layer.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: November 25, 2008
    Assignee: Touch Micro-System Technology Inc.
    Inventors: Hung-Yi Lin, Yao-Tian Chow, Pin-Ting Liu
  • Patent number: 7410821
    Abstract: A substrate having a sacrificial layer and a structural layer disposed on the front surface of the substrate is provided. Thereon an opening is formed on the back surface of the substrate and the sacrificial layer is exposed partially. A wet etching process is performed to etch the sacrificial layer via the opening to form a suspended structure. Finally, a gas injection process is performed. The gas injection process comprises blowing a gas on the suspended structure via the opening and consequently preventing the suspended structure from sticking to the substrate.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: August 12, 2008
    Assignee: Touch Micro-System Technology Inc.
    Inventors: Yao-Tian Chow, Pin-Ting Liu
  • Publication number: 20070105385
    Abstract: A substrate having a sacrificial layer and a structural layer disposed on the front surface of the substrate is provided. Thereon an opening is formed on the back surface of the substrate and the sacrificial layer is exposed partially. A wet etching process is performed to etch the sacrificial layer via the opening to form a suspended structure. Finally, a gas injection process is performed. The gas injection process comprises blowing a gas on the suspended structure via the opening and consequently preventing the suspended structure from sticking to the substrate.
    Type: Application
    Filed: March 22, 2006
    Publication date: May 10, 2007
    Inventors: Yao-Tian Chow, Pin-Ting Liu
  • Publication number: 20070066027
    Abstract: A substrate is provided and a plurality of trenches are formed in the front surface of the substrate. Then, a thermal oxide layer is formed on inner walls of the trenches and the front surface of the substrate. Subsequently, a first structural layer is formed on the thermal oxide layer, dopants are implanted into the first structural layer, a second structural layer is formed on the first structural layer, and an annealing process is performed to reduce the stress of the first and second structural layers. Following that, the first and second structural layers are patterned to form diaphragms. Finally, the second structural layer is mounted on a support wafer with a bonding layer, and the back surface of the substrate is etched by deep etching techniques to form back chambers corresponding to the diaphragms. Each back chamber has a vertical sidewall and partially exposes the first structural layer.
    Type: Application
    Filed: March 15, 2006
    Publication date: March 22, 2007
    Inventors: Hung-Yi Lin, Yao-Tian Chow, Pin-Ting Liu
  • Publication number: 20070048889
    Abstract: A wafer is provided, and a circuit layout including a first piezoresistive device layout and a second piezoresistive device layout is formed on the front surface of the wafer. The first piezoresistive device layout includes a plurality of first nodes and the second piezoresistive device layout includes a plurality of second nodes. Subsequently, a dielectric layer is formed on the circuit layout, and the dielectric layer is patterned to expose either the first nodes or the second nodes. Thereafter, a connection pattern is formed on the dielectric layer to electrically connect the first nodes or the second nodes.
    Type: Application
    Filed: November 18, 2005
    Publication date: March 1, 2007
    Inventors: Hung-Yi Lin, Pin-Ting Liu, Tsung-Hsun Tsai