Abstract: Bit lines coupled to a column of SRAM core cells in an array are sensed asynchronously using zero DC power with either differential sense amplifiers or single-ended amplifiers, according to the present invention. The differential sense amplifier embodiment includes a pair of cross-coupled series-connected PMOS and NMOS transistors connected between the power supplies. Each bit line is coupled to an NMOS gate in the transistor pair, and each PMOS gate is coupled to the drain-source connection of the other series-connected PMOS-NMOS pair. The PMOS gates and PMOS-NMOS drain-source connections define the sense amplifier complementary output signals, whose states are determined by the bit line states. The single-ended embodiment is implemented as a PMOS-NMOS transistor pair inverter connected between the power supplies. Each inverter input is coupled to a bit line, and the inverter outputs are the sense amplifier outputs.

Abstract: A retargetable SRAM system includes several block storage units that include a plurality of addressably selectable SRAM core cells, with a block single ended bit line driver coupleable to the output of each block storage unit to enhance voltage slew rate. To promote retargetability, digital (rather than analog) sense amplifiers are provided per each data output port. To minimize power-up crowbar current, the input of each unselected block bit line driver is forced to a "1" or "0" state. AMOS transistor coupled between the input port of each block bit line driver and an upper or lower system power supply has its gate input lead coupled to receive the system block select signal (or its complement). A desired SRAM core cell is accessed by specifying its row, column, and block address. A row select signal causes the cell output to be coupled to the input of the associated block bit line driver.