Patents by Inventor Pin-Yen TSAI

Pin-Yen TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12219880
    Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.
    Type: Grant
    Filed: March 4, 2024
    Date of Patent: February 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
  • Publication number: 20240256911
    Abstract: A method and a device for establishing a weak pattern severity model are provided. The method for establishing the weak pattern severity model includes the following steps. A plurality of weak patterns are obtained. A plurality of experiments are performed on each of the weak patterns with a plurality of parameter setting values of at least one process parameter to obtain a plurality of experimental results. According to the experimental results, a plurality of defects are obtained. According to the defects and the corresponding parameter setting values, a severity level of each of the weak patterns is analyzed. The weak patterns are labeled the severity levels. Machine learning is performed to train a weak pattern severity model.
    Type: Application
    Filed: March 20, 2023
    Publication date: August 1, 2024
    Inventors: Yan-Hsiu LIU, Pin-Yen TSAI
  • Publication number: 20240241498
    Abstract: A module for predicting semiconductor physical defects includes a defect diagnosis unit used to detect at least one failure circuit in a semiconductor circuit structure; an information acquisition unit used for obtaining a semiconductor mask layout for forming the semiconductor circuit structure, and obtaining a failure path configuration diagram corresponding to the failure circuits and the location information corresponding to the failure path configuration diagram; a feature classification unit used for extracting a plurality of cutting images of the failure path configuration diagram, and performing feature classification on these cutting images to obtain a plurality of image groups; and a failure risk assessment unit used for performing a risk pre-assessment to select at least one high-risk group therefrom, and performing a failure risk analysis to predict at least one high failure risk position in the semiconductor mask layout according to the analysis results and the location information.
    Type: Application
    Filed: February 24, 2023
    Publication date: July 18, 2024
    Inventors: Pin-Yen TSAI, Man-Ting PANG, Yi-Jung CHANG
  • Patent number: 12032891
    Abstract: The invention provides an operation method of a semiconductor system, which includes providing a system which includes a layout pattern to scanning electron microscope (SEM) pattern prediction model (LS model) and a novelty detection model (ND model), inputting a layout pattern to the ND model, and the ND model judges whether the layout pattern is a novel layout pattern, and if the layout pattern is confirmed as the novel layout pattern after judgment, performing a process step on the novel layout pattern to form an SEM (scanning electron microscope) pattern.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: July 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Yen Tsai, Yi-Jung Chang
  • Publication number: 20230195989
    Abstract: The invention provides an operation method of a semiconductor system, which includes providing a system which includes a layout pattern to scanning electron microscope (SEM) pattern prediction model (LS model) and a novelty detection model (ND model), inputting a layout pattern to the ND model, and the ND model judges whether the layout pattern is a novel layout pattern, and if the layout pattern is confirmed as the novel layout pattern after judgment, performing a process step on the novel layout pattern to form an SEM (scanning electron microscope) pattern.
    Type: Application
    Filed: January 12, 2022
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Yen Tsai, Yi-Jung Chang
  • Patent number: 10762618
    Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Yen Tsai, Hsu-Tang Liu, Yi-Jung Chang, Chun-Liang Hou
  • Publication number: 20200265573
    Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Inventors: Pin-Yen TSAI, Hsu-Tang LIU, Yi-Jung CHANG, Chun-Liang HOU