Patents by Inventor Pin-Yen TSAI

Pin-Yen TSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240206344
    Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.
    Type: Application
    Filed: March 4, 2024
    Publication date: June 20, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Hui-Hsien WEI, Wei-Chih WEN, Pin-Ren DAI, Chien-Min LEE, Sheng-Chih LAI, Han-Ting TSAI, Chung-Te LIN
  • Publication number: 20230195989
    Abstract: The invention provides an operation method of a semiconductor system, which includes providing a system which includes a layout pattern to scanning electron microscope (SEM) pattern prediction model (LS model) and a novelty detection model (ND model), inputting a layout pattern to the ND model, and the ND model judges whether the layout pattern is a novel layout pattern, and if the layout pattern is confirmed as the novel layout pattern after judgment, performing a process step on the novel layout pattern to form an SEM (scanning electron microscope) pattern.
    Type: Application
    Filed: January 12, 2022
    Publication date: June 22, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Yen Tsai, Yi-Jung Chang
  • Patent number: 10762618
    Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: September 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Pin-Yen Tsai, Hsu-Tang Liu, Yi-Jung Chang, Chun-Liang Hou
  • Publication number: 20200265573
    Abstract: A mask weak pattern recognition apparatus and a mask weak pattern recognition method are provided. The mask weak pattern recognition apparatus includes a receiving unit, an overlapping unit, an analyzing unit and a training unit. The receiving unit is used for receiving a mask layout and an inspection image of a mask. The overlapping unit is used for overlapping the mask layout and the inspection image to obtain an overlapped image. The analyzing unit is used for obtaining a plurality of risk patterns and a plurality of risk scores each of which corresponds one of the risk patterns according to the overlapped image. The training unit is used for training a recognition model according to the risk patterns and the risk scores.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Inventors: Pin-Yen TSAI, Hsu-Tang LIU, Yi-Jung CHANG, Chun-Liang HOU