Patents by Inventor Pin-Yuan Su

Pin-Yuan Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250174459
    Abstract: An assembly structure including a plurality of spacers, and a method of manufacturing the same are provided. The assembly structure includes a base material and a plurality of spacers disposed over the base material. Each of the plurality of spacers has a first lateral surface and a second lateral surface opposite to the first lateral surface. The second lateral surface is substantially parallel with the first lateral surface. A ratio of a height of the second lateral surface to a height of the first lateral surface is greater than 90%.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 29, 2025
    Inventor: PIN-YUAN SU
  • Publication number: 20250176158
    Abstract: An assembly structure including a plurality of spacers, and a method of manufacturing the same are provided. The assembly structure includes a base material and a plurality of spacers disposed over the base material. Each of the plurality of spacers has a first lateral surface and a second lateral surface opposite to the first lateral surface. The second lateral surface is substantially parallel with the first lateral surface. A ratio of a height of the second lateral surface to a height of the first lateral surface is greater than 90%.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 29, 2025
    Inventor: PIN-YUAN SU
  • Publication number: 20120175745
    Abstract: A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width.
    Type: Application
    Filed: January 6, 2011
    Publication date: July 12, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Pin Yuan Su, Weitung Yang, Yu-Chung Fang
  • Publication number: 20100317194
    Abstract: A method for fabricating openings is provided. A dielectric layer is formed on a substrate, and a first patterned mask layer is formed on the dielectric layer along a first direction. A second patterned mask layer is then formed on the dielectric layer along a second direction which intersects with the first direction. A portion of the dielectric layer is removed using the first patterned mask layer and the second patterned mask layer as a mask so as to from the openings. The dielectric layer, the first patterned mask layer and the second patterned mask layer have different etching selectivities.
    Type: Application
    Filed: June 12, 2009
    Publication date: December 16, 2010
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Pin-Yuan Su, Shu-Hao Hsu