Abstract: An oscillator circuit includes a comparator having first and second inputs, the first input configured to be coupled to a reference voltage. The oscillator circuit also includes a capacitor and a first current source. The capacitor is coupled between the second input and ground. The first current source is coupled between a supply voltage terminal and the capacitor. The first current source is configured to generate a current to the capacitor that is proportional to absolute temperature.

Abstract: An oscillator circuit includes a comparator having first and second inputs, the first input configured to be coupled to a reference voltage. The oscillator circuit also includes a capacitor and a first current source. The capacitor is coupled between the second input and ground. The first current source is coupled between a supply voltage terminal and the capacitor. The first current source is configured to generate a current to the capacitor that is proportional to absolute temperature.

Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Abstract: Integrated circuits having self-calibrating oscillators, and methods of operating the same are disclosed. A disclosed example integrated circuit includes a clock generator, a comparator having a first input connected to an output of the clock generator and a second input connected to a reference voltage, a calibration done detector having an input connected to an output of the comparator and an output communicatively coupled to a calibration code register.

Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

Abstract: Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

Abstract: A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.

Abstract: A processor having binary switches is configured to operate at a predetermined probability value that the logical value of each switch is correct. A supply voltage is coupled to the binary switches. A randomized signal detector is configured to detect a randomized signal, which may be amplified to a predetermined level if the randomized signal is low. A computing element outputs a probabilistic binary bit having a 0 or 1 with a predetermined probability value of being correct in correspondence with the supply voltage and/or an amplification level of a noise signal. Subsequently, an application executed by the processor receives the probabilistic binary bit for one or more additional operations. By operating on the probabilistic binary bits instead of conventional deterministic bits, the processor consumes less energy and completes its execution faster. For battery-powered portable electronic devices, use of processor configured for probabilistic binary bits substantially lengthens battery life.