Patents by Inventor Ping Chao

Ping Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12367374
    Abstract: A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: July 22, 2025
    Assignee: NEUCHIPS CORPORATION
    Inventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
  • Publication number: 20250176203
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device comprises a substrate, a plurality of fin structures and a gate structure. The fin structures are disposed on the substrate. The gate structure is formed on the fin structures and is substantially perpendicular to the fin structures. Each of the fin structures includes a first source/drain region and a second source/drain region, and the gate structure is located between the first source/drain region and the second source/drain region, and at least one of the fin structures is electrically floated between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: November 27, 2023
    Publication date: May 29, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Cheng Tsou, Yi-Ping Chao, Jung-Chi Jeng, Chen-Chieh CHIANG
  • Patent number: 12301186
    Abstract: A differential amplifier is provided. The differential amplifier includes a first load, a second load, a current source, a differential pair circuit, a first and a second switch circuit. The differential pair circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first switch circuit controls the first and the second transistors, and the second switch circuit controls the third and the fourth transistors. Through the control and selection of the first and second switch circuits, a differential pair is selected in the differential pair circuit to receive and process a first input signal and a second input signal for signal.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hao Chang, Manoj M. Mhala, Calvin Yi-Ping Chao
  • Publication number: 20250130036
    Abstract: A method includes generating light pulses by an illumination source toward an object; collecting the light pulses reflected from the object by an image sensor; generating a first signal-time plot of a sensor signal by the image sensor; generating a second signal-time plot of an index signal, wherein the second signal-time plot of the index signal comprises pulsed signals corresponding to the light pulses, respectively; collecting data from selected time periods of the first signal-time plot of the sensor signal, wherein the selected time periods of the first signal-time plot of the sensor signal are the same as time periods of the light pulses in the second signal-time plot of the index signal; and generating a third signal-time plot of an output signal based on the collected data.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 24, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Yi TU, Meng-Hsiu WU, Shang-Fu YEH, Chiao-Yi HUANG, Calvin Yi-Ping CHAO
  • Publication number: 20250056894
    Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate including a semiconductor substrate and an insulator layer over the semiconductor substrate; forming a trench through the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench and over an upper surface of the second region; thickening the initial epitaxial layer to form an epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: YUNG-CHIH TSAI, CHIH-PING CHAO, CHUN-HUNG CHEN, SHAOQIANG ZHANG, KUAN-LIANG LIU, CHUN-PEI WU, ALEXANDER KALNITSKY
  • Patent number: 12194093
    Abstract: Methods are provided herein for determining and administering optimized dosing of therapeutic anti-CD47 agents, in a schedule that provides safe escalation of dose while achieving a therapeutic level in a clinically effective period of time. The methods can comprise the steps of clearance, escalation, and maintenance. In one embodiment the dosing regimen administers an initial (i) sub-therapeutic dose of an anti-CD47 agent or (ii) a cytoreductive therapy to achieve a safe level of circulating tumor cells for subsequent treatment (clearance); escalating the dose of an anti-CD47 agent until a therapeutic dose is reached (escalation); and maintaining the therapeutic dose for a period of time sufficient to reduce tumor cells in the bone marrow of the patient (maintenance). In an alternative dosing regimen, a patient determined to have a safe level of circulating tumor cells at presentation is treated by the steps of escalation and maintenance without initial clearance.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: January 14, 2025
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Forty Seven, LLC
    Inventors: Ravindra Majeti, Mark Ping Chao, Jie Liu, Jens-Peter Volkmer, Irving L. Weissman
  • Publication number: 20250006528
    Abstract: A container for receiving a semiconductor device is provided. In one embodiment, the wafer holder assembly includes a first wafer holder with a plurality of first fingers arranged in a first common horizontal plane and a second wafer holder with a plurality of second fingers arranged in a second common horizontal plane. The first wafer holder and the second holder are configured to move relative to each other in a vertical direction, and the first wafer holder and the second holder are configured to rotate relative to each other around a vertical axis.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 2, 2025
    Inventors: CHENG-YOU TAI, LING-SUNG WANG, CHEN-CHIEH CHIANG, JUNG-CHI JENG, Yi PING CHAO, ZHI-HONG CHUNG
  • Patent number: 12159873
    Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Chih Tsai, Chih-Ping Chao, Chun-Hung Chen, Shaoqiang Zhang, Kuan-Liang Liu, Chun-Pei Wu, Alexander Kalnitsky
  • Patent number: 12113071
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a polysilicon layer arranged on an upper surface of a base substrate. A dielectric layer is arranged over the polysilicon layer, and an active semiconductor layer is arranged over the dielectric layer. A semiconductor material is arranged vertically on the upper surface of the base substrate and laterally beside the active semiconductor layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee, Chih-Ping Chao, Alexander Kalnitsky
  • Publication number: 20240332306
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an epitaxial layer arranged on a semiconductor body. A trap-rich layer is arranged on the epitaxial layer, a dielectric layer is arranged on the trap-rich layer, and an active semiconductor layer is arranged on the dielectric layer. A semiconductor material is arranged on the epitaxial layer and laterally beside the active semiconductor layer. The epitaxial layer continuously extends from directly below the trap-rich layer to directly below the semiconductor material.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, Szu-Yu Wang, Chia-Shiung Tsai, Ru-Liang Lee, Chih-Ping Chao, Alexander Kalnitsky
  • Publication number: 20240329805
    Abstract: The subject invention is a method of inputting a character and associated computer program product, cloud system, and electronic device, and a method of indexing a character. The method of inputting a character includes: receiving a command which indicates an element; receiving a command to select one of a plurality of features which classify a group of roots associated with the element; displaying a form list in response to the command; and receiving a command to select a form in the form list to complete an input of a character.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: POR-SEN JAW, YIN-PING CHAO
  • Patent number: 12092767
    Abstract: A method of a sensing device, comprising steps of emitting, by a light source of the sensing device, a light pulse in each of n cycles; measuring, by a single photon avalanche diodes array of the sensing device, a time-of-flight value with a resolution of m in each of the n cycles to generate n raw data frames based on a reflected light of the light pulse; performing, by a pre-processing circuit of the sensing device, a pre-processing operation to n raw data frames to generate k pre-processed data frames, wherein m, n and k are natural numbers, and k is smaller than n; and generating, by post-processor of the sensing device, a histogram according to the k pre-processed data frames and analyzing the histogram to output a depth result.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
  • Publication number: 20240218077
    Abstract: Methods, kits, and compositions are provided herein that can be used to treat CD20+ cancer using an anti-CD47 agent such as an antibody. The anti-CD47 agent can be used alone or in combination with one or more additional agent such as an anti-CD20 antibody.
    Type: Application
    Filed: December 19, 2023
    Publication date: July 4, 2024
    Inventors: Mark Ping Chao, Chris Hidemi Mizufune Takimoto, Jens-Peter Volkmer
  • Publication number: 20240150461
    Abstract: Methods, kits, and compositions are provided herein that can be used to treat ovarian cancer using an anti-CD47 antibody. The anti-CD47 antibody can be used alone or in combination with one or more additional agent such as chemotherapy.
    Type: Application
    Filed: September 27, 2023
    Publication date: May 9, 2024
    Inventors: Chris Hidemi Mizufune Takimoto, Mark Ping Chao, Jens-Peter Volkmer
  • Publication number: 20240124578
    Abstract: Methods, kits, and compositions are provided herein that can be used to treat hematopoietic disorders using an anti-CD47 agent such as an antibody and a hypomethylating agent, such as azacitidine.
    Type: Application
    Filed: September 13, 2023
    Publication date: April 18, 2024
    Inventors: Yinuo Cao, Mark Ping Chao, Ravindra Majeti, Roy Louis Maute, Chris Hidemi Mizufune Takimoto, Kelly Tran
  • Patent number: 11891450
    Abstract: Methods, kits, and compositions are provided herein that can be used to treat CD20+ cancer using an anti-CD47 agent such as an antibody. The anti-CD47 agent can be used alone or in combination with one or more additional agent such as an anti-CD20 antibody.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 6, 2024
    Assignee: Forty Seven, Inc.
    Inventors: Mark Ping Chao, Chris Hidemi Mizufune Takimoto, Jens-Peter Volkmer
  • Publication number: 20230375611
    Abstract: A method for testing semiconductor devices is disclosed, which includes: obtaining a result measured on a semiconductor device in one of a set of tests; comparing the result with a maximum value determined among respective results that were previously measured in one or more of the set of tests and a minimum value determined among respective results that were previously measured in one or more of the set of tests; determining, based on the comparison between the first result and the maximum and minimum values, whether to update the maximum and minimum values to calculate a delta value; comparing the delta value with a noise threshold value; determining based on the comparison between the delta value and the noise threshold value, whether to update a value of a timer; determining that the value of the timer satisfies a timer threshold; and determining that the semiconductor device incurs noise.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hao Chang, Meng-Hsiu Wu, Chiao-Yi Huang, Manoj Mhala, Calvin Yi-Ping Chao
  • Patent number: 11802153
    Abstract: Methods, kits, and compositions are provided herein that can be used to treat ovarian cancer using an anti-CD47 antibody. The anti-CD47 antibody can be used alone or in combination with one or more additional agent such as chemotherapy.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: October 31, 2023
    Assignee: Forty Seven, Inc.
    Inventors: Chris Hidemi Mizufune Takimoto, Mark Ping Chao, Jens-Peter Volkmer
  • Patent number: 11795223
    Abstract: Methods, kits, and compositions are provided herein that can be used to treat hematopoietic disorders using an anti-CD47 agent such as an antibody and a hypomethylating agent, such as azacitidine.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 24, 2023
    Assignee: Forty Seven, Inc.
    Inventors: Yinuo Cao, Mark Ping Chao, Ravindra Majeti, Roy Louis Maute, Chris Hidemi Mizufune Takimoto, Kelly Tran
  • Patent number: 11782839
    Abstract: A feature map caching method of a convolutional neural network includes a connection analyzing step and a plurality of layer operation steps. The connection analyzing step is for analyzing a network to establish a convolutional neural network connection list. The convolutional neural network connection list includes a plurality of tensors and a plurality of layer operation coefficients. Each of the layer operation coefficients includes a step index, at least one input operand label and an output operand label. The step index as a processing order for the layer operation step. At least one of the layer operation steps is for flushing at least one of the tensors in a cache according to a distance between the at least one of the layer operation steps and a future layer operation step of the layer operation steps. The distance is calculated according to the convolutional neural network connection list.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: October 10, 2023
    Assignee: NEUCHIPS CORPORATION
    Inventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin