Patents by Inventor Ping Chao
Ping Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12367374Abstract: A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.Type: GrantFiled: April 13, 2022Date of Patent: July 22, 2025Assignee: NEUCHIPS CORPORATIONInventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
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Patent number: 11782839Abstract: A feature map caching method of a convolutional neural network includes a connection analyzing step and a plurality of layer operation steps. The connection analyzing step is for analyzing a network to establish a convolutional neural network connection list. The convolutional neural network connection list includes a plurality of tensors and a plurality of layer operation coefficients. Each of the layer operation coefficients includes a step index, at least one input operand label and an output operand label. The step index as a processing order for the layer operation step. At least one of the layer operation steps is for flushing at least one of the tensors in a cache according to a distance between the at least one of the layer operation steps and a future layer operation step of the layer operation steps. The distance is calculated according to the convolutional neural network connection list.Type: GrantFiled: August 19, 2019Date of Patent: October 10, 2023Assignee: NEUCHIPS CORPORATIONInventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
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Patent number: 11467968Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a number of a plurality of input channels of a plurality of input feature maps, an input feature map tile size, a number of a plurality of output channels of a plurality of output feature maps and an output feature map tile size for a convolutional layer operation. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation. The convolution calculating step is for performing the convolutional layer operation with the input feature maps to produce the output feature maps according to a memory-adaptive processing technique, and the memory-adaptive processing technique includes a dividing step and an output-group-first processing step.Type: GrantFiled: February 26, 2021Date of Patent: October 11, 2022Assignee: NEUCHIPS CORPORATIONInventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
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Publication number: 20220237430Abstract: A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Inventors: Ping CHAO, Chao-Yang KAO, Youn-Long LIN
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Patent number: 11051045Abstract: A method and a circuit for adaptive loop filtering in a video coding system are described. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.Type: GrantFiled: March 11, 2020Date of Patent: June 29, 2021Assignee: MEDIATEK INC.Inventors: Ping Chao, Chih-Ming Wang, Yung-Chang Chang
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Publication number: 20210182204Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a number of a plurality of input channels of a plurality of input feature maps, an input feature map tile size, a number of a plurality of output channels of a plurality of output feature maps and an output feature map tile size for a convolutional layer operation. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation. The convolution calculating step is for performing the convolutional layer operation with the input feature maps to produce the output feature maps according to a memory-adaptive processing technique, and the memory-adaptive processing technique includes a dividing step and an output-group-first processing step.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Inventors: Ping CHAO, Chao-Yang KAO, Youn-Long LIN
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Patent number: 10963390Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a plurality of input channels of an input feature map tile and a plurality of output channels of an output feature map tile for a convolutional layer operation of the convolutional neural network. The size relation counting step is for obtaining a cache free space size in a feature map cache and counting a size relation among a total input size, a total output size and the cache free space size of the feature map cache. The convolution calculating step is for performing the convolutional layer operation according to a memory-adaptive processing technique.Type: GrantFiled: August 7, 2019Date of Patent: March 30, 2021Assignee: NEUCHIPS CORPORATIONInventors: Ping Chao, Chao-Yang Kao, Youn-Long Lin
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HARMONIC DENSELY CONNECTING METHOD OF BLOCK OF CONVOLUTIONAL NEURAL NETWORK MODEL AND SYSTEM THEREOF
Publication number: 20200410353Abstract: A harmonic densely connecting method includes an input step, a plurality of layer operation steps and an output step. The input step is for storing an original input tensor of the block into a memory. Each of the layer operation steps includes a layer-input tensor concatenating step and a convolution operation step. The layer-input tensor concatenating step is for selecting at least one layer-input element tensor of a layer-input set from the memory according to an input connection rule. When a number of the at least one layer-input element tensor is greater than 1, concatenating all of the layer-input element tensors and producing a layer-input tensor. The convolution operation step is for calculating a convolution operation to produce at least one result tensor and then storing the at least one result tensor into the memory. The output step is for outputting a block output.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Ping CHAO, Chao-Yang KAO, Youn-Long LIN -
Publication number: 20200213624Abstract: Aspects of the disclosure provide a method and a circuit for adaptive loop filtering in a video coding system. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Applicant: MEDIATEK INC.Inventors: Ping Chao, Chih-Ming Wang, Yung-Chang Chang
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Patent number: 10609417Abstract: A method and a circuit for adaptive loop filtering in a video coding system are described. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.Type: GrantFiled: May 16, 2017Date of Patent: March 31, 2020Assignee: MEDIATEK INC.Inventors: Ping Chao, Chih-Ming Wang, Yung-Chang Chang
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Publication number: 20200065250Abstract: A feature map caching method of a convolutional neural network includes a connection analyzing step and a plurality of layer operation steps. The connection analyzing step is for analyzing a network to establish a convolutional neural network connection list. The convolutional neural network connection list includes a plurality of tensors and a plurality of layer operation coefficients. Each of the layer operation coefficients includes a step index, at least one input operand label and an output operand label. The step index as a processing order for the layer operation step. At least one of the layer operation steps is for flushing at least one of the tensors in a cache according to a distance between the at least one of the layer operation steps and a future layer operation step of the layer operation steps. The distance is calculated according to the convolutional neural network connection list.Type: ApplicationFiled: August 19, 2019Publication date: February 27, 2020Inventors: Ping CHAO, Chao-Yang KAO, Youn-Long LIN
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Publication number: 20200065251Abstract: A memory-adaptive processing method for a convolutional neural network includes a feature map counting step, a size relation counting step and a convolution calculating step. The feature map counting step is for counting a plurality of input channels of an input feature map tile and a plurality of output channels of an output feature map tile for a convolutional layer operation of the convolutional neural network. The size relation counting step is for obtaining a cache free space size in a feature reap cache and counting a size relation among a total input size, a total output size and the cache free space size of the feature map cache. The convolution calculating step is for performing the convolutional layer operation according to a memory-adaptive processing technique.Type: ApplicationFiled: August 7, 2019Publication date: February 27, 2020Inventors: Ping CHAO, Chao-Yang KAO, Youn-Long LIN
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Patent number: 10418002Abstract: Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.Type: GrantFiled: October 17, 2017Date of Patent: September 17, 2019Assignee: MEDIATEK INC.Inventors: Ping Chao, Ting-An Lin, Tung-Hsing Wu, Kung-Tsun Yang, Wan-Yu Chen, Chuang-Chi Chiou, Ping-yao Wang, Wei-Gen Wu, Hsin-Hao Chung, Chih-Ming Wang, Han-Liang Chou, Chung Hsien Lee, Yung-Chang Chang, Chi-Cheng Ju
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Patent number: 10397588Abstract: A method and apparatus of sharing an on-chip buffer or cache memory for a video coding system using coding modes including Inter prediction mode or Intra Block Copy (IntraBC) mode are disclosed. At least partial pre-deblocking reconstructed video data of a current picture is stored in an on-chip buffer or cache memory. If the current block is coded using IntraBC mode, the pre-deblocking reconstructed video data of the current picture stored in the on-chip buffer or cache memory are used to derive IntraBC prediction for the current block. In some embodiments, if the current block is coded using Inter prediction mode, Inter reference video data from the previous picture stored in the on-chip buffer or cache memory are used to derive Inter prediction for the current block. In another embodiment, the motion compensation/motion estimation unit is shared by the two modes.Type: GrantFiled: June 3, 2016Date of Patent: August 27, 2019Assignee: MEDIATEK INC.Inventors: Tzu-Der Chuang, Ping Chao, Ching-Yeh Chen, Yu-Chen Sun, Chih-Ming Wang, Chia-Yun Cheng, Han-Liang Chou, Yu-Wen Huang
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Patent number: 10366467Abstract: A method for storing data of an image frame into a frame buffer includes at least the following steps: dividing the image frame into a plurality of access units, each having at least one encoding unit, wherein each encoding unit is a unit for data compression; and performing the data compression upon each encoding unit of the image frame, and generating an output bitstream to the frame buffer based on a data compression result of the encoding unit. A processing result of each access unit includes each output bitstream of the at least one encoding unit included in the access unit; a plurality of processing results of the access units are stored in a plurality of storage spaces allocated in the frame buffer, respectively; and a size of each of the storage spaces is equal to a size of a corresponding access unit.Type: GrantFiled: August 16, 2017Date of Patent: July 30, 2019Assignee: MEDIATEK INC.Inventors: Tsu-Ming Liu, Ping Chao, Yung-Chang Chang
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Patent number: 10306246Abstract: A method and apparatus for loop filter processing of reconstructed video data for a video coding system are disclosed. The system receives reconstructed video data for an image unit. The loop filter processing is applied to reconstructed pixels above a deblocking boundary of the current CTU. In order to reduce line buffer requirement and/or to reduce loop filter switching for image units, the sample adaptive offset (SAO) parameter boundary and spatial-loop-filter restricted boundary for the luma and chroma components are determined by global consideration. In one embodiment, the SAO parameter boundary and the spatial-loop-filter restricted boundary are aligned for the luma and chroma components respectively. In another embodiment, the SAO parameter boundary and the spatial-loop-filter restricted boundary for the luma and chroma components are all aligned.Type: GrantFiled: January 29, 2016Date of Patent: May 28, 2019Assignee: MEDIATEK INC.Inventors: Ping Chao, Huei-Min Lin, Chih-Ming Wang, Yung-Chang Chang
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Patent number: 10134107Abstract: A data arrangement method includes following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer according to a block-based scan order of the picture. The picture includes a plurality of data blocks, and the block-based scan order includes a raster-scan order for the data blocks. At least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, M and N are positive integers, M is not divisible by N, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer.Type: GrantFiled: March 27, 2014Date of Patent: November 20, 2018Assignee: MEDIATEK INC.Inventors: Chun-Chia Chen, Chi-Cheng Ju, Yung-Chang Chang, Ping Chao
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Publication number: 20180139464Abstract: Aspects of the disclosure provide a video decoding system. The video decoding system can include a decoder core configured to selectively decode independently decodable tiles in a picture, each tile including largest coding units (LCUs) each associated with a pair of picture-based (X, Y) coordinates or tile-based (X, Y) coordinates, and memory management circuitry configured to translate one or two coordinates of a current LCU to generate one or two translated coordinates, and to determine a target memory space storing reference data for decoding the current LCU based on the one or two translated coordinates.Type: ApplicationFiled: November 3, 2017Publication date: May 17, 2018Applicant: MEDIATEK INC.Inventors: Min-Hao CHIU, Ping Chao, Chia-Hung Kao, Huei-Min Lin, Hsiu-Yi Lin, Chi-Hung Chen, Chia-Yun Cheng, Chih-Ming Wang, Yung-Chang Chang
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Publication number: 20180108331Abstract: Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.Type: ApplicationFiled: October 17, 2017Publication date: April 19, 2018Applicant: MEDIATEK INC.Inventors: Ping CHAO, Ting-An LIN, Tung-Hsing WU, Kung-Tsun YANG, Wan-Yu CHEN, Chuang-Chi CHIOU, Ping-yao WANG, Wei-Gen WU, Hsin-Hao CHUNG, Chih-Ming WANG, Han-Liang CHOU, Chung Hsien LEE, Yung-Chang CHANG, Chi-Cheng JU
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Publication number: 20180107616Abstract: Aspects of the disclosure provide a method and device for storing an input image into a memory. The disclosure describes allocating one or more frame buffers in the memory. The disclosure further describes dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer. The disclosure also describes compressing the access units into compressed access units and storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.Type: ApplicationFiled: October 18, 2017Publication date: April 19, 2018Applicant: MEDIATEK INC.Inventors: Ping CHAO, Chih-Wen YANG, Chih-Ming WANG