Patents by Inventor Ping-Che Lee

Ping-Che Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260110074
    Abstract: Methods and systems are disclosed for depositing aluminum nitride thin films by reactive sputtering using a sequence of negative-polarity voltage pulses applied to an aluminum target, followed by a positive-polarity voltage pulse. HiPIMS-type waveforms may be used to implement the negative-polarity and/or positive-polarity pulses. A substrate is provided in a sputtering chamber, a process gas comprising an inert gas and a nitrogen-containing gas is introduced, and the chamber is maintained at a reduced pressure. A sequence of negative-polarity voltage pulses is applied to an aluminum target, followed by application of a positive-polarity voltage pulse to the target. The disclosed methods and systems can produce aluminum nitride thin films exhibiting improved crystallinity, thermal conductivity, and surface quality at reduced deposition temperatures (e.g., below 200° C.) and with deposition rates of at least about 50 nm/min suitable for industrial applications.
    Type: Application
    Filed: October 22, 2025
    Publication date: April 23, 2026
    Inventors: Andrew Kummel, Ping-Che Lee, Diego Contreras Mora, Dohyun Go, Satish Kumar, Mingeun Choi
  • Publication number: 20200003802
    Abstract: A testing socket including a circuit board having a by-pass circuit and testing pins is provided. The circuit board includes a core dielectric layer, a power plane, and a ground plane. The core dielectric layer has a first surface and a second surface opposite to the first surface. The power plane is located on the first surface of the core dielectric layer, and the power plane is electrically connected to the by-pass circuit. The ground plane is located on the second surface of the core dielectric layer. The testing pins penetrates the circuit board, wherein two ends of each the testing pins are protruding out of the circuit board, a first group of the testing pins are electrically connected to the power plane, and a second group of the testing pins are electrically isolated from the power plane.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 2, 2020
    Applicant: Powertech Technology Inc.
    Inventors: Ping-Che Lee, Ying-Tang Chao
  • Publication number: 20190052489
    Abstract: The communication interface including a data encoder. The data encoder receives a data package which has at least one first output signal with N bits, generates and outputs at least one transmitting signal during one period of a reference clock signal and determining a voltage level of the transmitting signal according to a logic value of the first output signal, wherein N is an integer larger than 1.
    Type: Application
    Filed: August 8, 2017
    Publication date: February 14, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Chih-Hui Yeh, Ping-Che Lee, Fu-Hsiang Chang
  • Patent number: 10021784
    Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 10, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Ping-Che Lee, Ying-Tang Chao