Patents by Inventor Ping-Cheng Chen

Ping-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240345764
    Abstract: A memory control circuit unit, a memory storage device, and a parameter updating method are disclosed. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The memory interface is configured to be coupled to a rewritable non-volatile memory module. The memory management circuit is configured to detect system status and activate an interface parameter updating operation in response to the system status meeting a target condition. The memory management circuit is further configured to update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 17, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Patent number: 12008239
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: June 11, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Publication number: 20240184449
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.
    Type: Application
    Filed: January 9, 2023
    Publication date: June 6, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
  • Publication number: 20240086109
    Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command from a host system, and the write command including first data; checking a status of a first physical programming unit in a first physical erasing unit; in response to the status of the first physical programming unit being a first status, sending a first command sequence to a rewritable non-volatile memory module, and the first command sequence being configured to instruct the rewritable non-volatile memory module to store at least part of the first data to the first physical programming unit.
    Type: Application
    Filed: October 17, 2022
    Publication date: March 14, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei-Cheng Li, Yu-Chung Shen, Jia-Li Xu, Ping-Cheng Chen
  • Patent number: 11196455
    Abstract: An isolation estimation system includes a transmitter device, a first receiver device, a second receiver device, and a processor circuit. The transmitter device adopts a first communication technology. The transmitter device is configured to transmit a transmitting signal to the first receiving device. The second receiver device is configured to acquire a leakage signal power spectral density of a leakage signal corresponding to the transmitting signal. The second receiver device adopts a second communication technology. A bandwidth of the second communication technology is narrower than a bandwidth of the first communication technology, and the second communication technology supports a frequency hopping process. The processor circuit is configured to calculate isolation according to a signal-in-air power spectral density of the transmitting signal and the leakage signal power spectral density. The isolation is for determining whether to adjust the transmitter device.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ping-Cheng Chen, Chih-Hung Tsai
  • Patent number: 11101822
    Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving first data and second data from a host system; generating a first array error correcting code based on the first data, and generating a second array error correcting code based on the second data; programming a first group including the first array error correcting code into a first chip enable group by using a first programming mode; and programming a second group including the second array error correcting code into a second chip enable group by using a second programming mode.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 24, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ping-Cheng Chen