Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A large area deposition type additive manufacturing equipment is disclosed. The large area deposition type additive manufacturing equipment includes a light source module, a dynamic photomask module, a raw material tank and a deposition module. The light source module includes a plurality of light emitting members, a light diffusion member, a light enhancement member and a light emitting angle limiter. Light emitted from the light emitting members passes through the light diffusion member, the light enhancement member and the light emitting angle limiter to become a collimated curing light. The collimated curing light travels through a transparent member of the raw material tank and a dynamic photomask module to reach liquid photocurable material in the raw material tank, thereby curing the liquid photocurable material. The angle of emitted light ranges within ±30° with respect to a normal line of an incident plane of the light source module.

Abstract: A mask characterization method comprises measuring an interference signal of a reflection or transmission mask for use in lithography; and determining a quality metric for the reflection or transmission mask based on the interference signal. A mask characterization apparatus comprises a light source arranged to illuminate a reflective or transmissive mask with light whereby mask-reflected or mask-transmitted light is generated; an optical grating arranged to convert the mask-reflected or mask-transmitted light into an interference pattern; and an optical detector array arranged to generate an interference signal by measuring the interference pattern.

Abstract: A memory control circuit unit, a memory storage device, and a parameter updating method are disclosed. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The memory interface is configured to be coupled to a rewritable non-volatile memory module. The memory management circuit is configured to detect system status and activate an interface parameter updating operation in response to the system status meeting a target condition. The memory management circuit is further configured to update at least one interface parameter used by at least one of the memory interface and the rewritable non-volatile memory module during the interface parameter updating operation.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, and an absorber layer disposed on the capping layer. The absorber layer includes a base material made of one or more of a Cr based material, an Ir based material, a Pt based material, or Co based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command from a host system, and the write command including first data; checking a status of a first physical programming unit in a first physical erasing unit; in response to the status of the first physical programming unit being a first status, sending a first command sequence to a rewritable non-volatile memory module, and the first command sequence being configured to instruct the rewritable non-volatile memory module to store at least part of the first data to the first physical programming unit.

Abstract: An isolation estimation system includes a transmitter device, a first receiver device, a second receiver device, and a processor circuit. The transmitter device adopts a first communication technology. The transmitter device is configured to transmit a transmitting signal to the first receiving device. The second receiver device is configured to acquire a leakage signal power spectral density of a leakage signal corresponding to the transmitting signal. The second receiver device adopts a second communication technology. A bandwidth of the second communication technology is narrower than a bandwidth of the first communication technology, and the second communication technology supports a frequency hopping process. The processor circuit is configured to calculate isolation according to a signal-in-air power spectral density of the transmitting signal and the leakage signal power spectral density. The isolation is for determining whether to adjust the transmitter device.

Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving first data and second data from a host system; generating a first array error correcting code based on the first data, and generating a second array error correcting code based on the second data; programming a first group including the first array error correcting code into a first chip enable group by using a first programming mode; and programming a second group including the second array error correcting code into a second chip enable group by using a second programming mode.