Patents by Inventor Ping-Cheng HAN

Ping-Cheng HAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230261083
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.
    Type: Application
    Filed: April 20, 2023
    Publication date: August 17, 2023
    Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH
  • Patent number: 11670699
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 6, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Edward Yi Chang, Shih-Chien Liu, Chung-Kai Huang, Chia-Hsun Wu, Ping-Cheng Han, Yueh-Chin Lin, Ting-En Hsieh
  • Publication number: 20200203499
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH
  • Publication number: 20180175185
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a recess, a charge trapping layer, a ferroelectric material layer, a gate, a source and a drain. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The barrier layer has a recess, and a portion of the barrier layer under the recess has a thickness. The source and the drain are disposed on the barrier layer. The charge trapping layer covers the bottom of the recess. The ferroelectric material is disposed on the charge trapping layer. The gate is disposed on the ferroelectric material.
    Type: Application
    Filed: July 10, 2017
    Publication date: June 21, 2018
    Inventors: Edward Yi CHANG, Shih-Chien LIU, Chung-Kai HUANG, Chia-Hsun WU, Ping-Cheng HAN, Yueh-Chin LIN, Ting-En HSIEH