Patents by Inventor Ping Chet Tan

Ping Chet Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9748197
    Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 29, 2017
    Assignee: Altera Corporation
    Inventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
  • Publication number: 20160307868
    Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.
    Type: Application
    Filed: June 24, 2016
    Publication date: October 20, 2016
    Inventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
  • Patent number: 9401287
    Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: July 26, 2016
    Assignee: Altera Corporation
    Inventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
  • Patent number: 9337240
    Abstract: A lead frame for an integrated circuit (IC) package is disclosed. The lead frame includes a center region and a plurality of lead fingers surrounding the center region. The plurality of lead fingers that surrounds the center region defines a periphery region around the center region. A portion of the plurality of lead fingers extends from the center region to hold the center region in place. Tie bars that are typically used to hold the center region in place may not be included in the lead frame.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 10, 2016
    Assignee: Altera Corporation
    Inventors: Guan Khai Lee, Loon Kwang Tan, Ping Chet Tan, Pheak Ti Teh
  • Patent number: 9330997
    Abstract: A heat spreader structure includes a planar portion and a slanted portion. The slanted portion extends at an angle from an edge of the planar portion. The first slanted portion includes a first slot. A second heat spreader structure includes a planar member, a first edge member and a second edge member. The first edge member extends only perpendicularly from a first edge of the planar member whereas the second edge member extends from the second edge of the planar member and has a slanted surface with respect to that of the planar member. In addition to that, the first and second heat spreader structure may be formed using different manufacturing methods.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 3, 2016
    Assignee: Altera Corporation
    Inventors: Ken Beng Lim, Myung June Lee, Yuan Li, Ping Chet Tan
  • Publication number: 20150228506
    Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 13, 2015
    Applicant: Altera Corporation
    Inventors: Loon Kwang Tan, Yuanlin Xie, Ping Chet Tan
  • Patent number: 9076776
    Abstract: Provided is a lead frame package with stand-off legs to prevent the die attach pad (DAP), which is part of the package substrate, to tilt or shift from its original position during the molding process. Also provided are methods for assembling such lead frame packages into various integrated circuit (IC) packages. Compared to conventional lead frame packages without stand-off legs, the lead frame packages of the present invention have less aesthetic and functional defects, thereby leading to an increase in product reliability and yield.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: July 7, 2015
    Assignee: Altera Corporation
    Inventors: Ken Beng Lim, Ping Chet Tan